Datasheet ADIS16467 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Precision MEMS IMU Module |
| Pages / Page | 34 / 5 — ADIS16467. Preliminary Technical Data. Parameter Test. … |
| Revision | B |
| File Format / Size | PDF / 600 Kb |
| Document Language | English |
ADIS16467. Preliminary Technical Data. Parameter Test. Conditions/Comments. Min. Typ. Max. Unit
Model Line for this Datasheet
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ADIS16467 Preliminary Technical Data Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS4 Input Voltage High, VIH 2.0 V Low, VIL 0.8 V RST Pulse Width 1 μs CS Wake-Up Pulse Width 20 μs Input Current Logic 1, IIH VIH = 3.3 V 10 μA Logic 0, IIL VIL = 0 V All Pins Except RST 10 μA RST Pin 0.33 mA Input Capacitance, CIN 10 pF DIGITAL OUTPUTS Output Voltage High, VOH ISOURCE = 0.5 mA 2.4 V Low, VOL ISINK = 2.0 mA 0.4 V FLASH MEMORY Endurance5 10000 Cycles Data Retention6 TJ = 85°C 20 Years FUNCTIONAL TIMES7 Time until data is available Power-On Start-Up Time 259 ms Reset Recovery Time8 GLOB_CMD, Bit 7 = 1 (see Table 113) 198 ms Factory Calibration Restore GLOB_CMD, Bit 1 = 1 (see Table 113) 143 ms Flash Memory Backup GLOB_CMD, Bit 3 = 1 (see Table 113) 72 ms Flash Memory Test Time GLOB_CMD, Bit 4 = 1 (see Table 113) 32 ms Self Test Time9 GLOB_CMD, Bit 2 = 1 (see Table 113) 20 ms CONVERSION RATE 2000 SPS Initial Clock Accuracy 3 % Sync Input Clock 1.9 2.1 kHz POWER SUPPLY, VDD Operating voltage range 3.0 3.6 V Power Supply Current10 Normal mode, VDD = 3.3 V 44 55 mA 1 The scale factors for each range are listed in Table 11. 2 This measurement is based on the deviation from a best fit linear model. 3 All specifications associated with the accelerometers relate to the full-scale range of ±8 g, unless otherwise noted. 4 The digital input/output signals use a 3.3 V system. 5 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −40°C, +25°C, +85°C, and +125°C. 6 The data retention specification assumes a junction temperature (TJ) of 85°C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ. 7 These times do not include thermal settling and internal filter response times, which may affect overall accuracy. 8 The RST line must be in a low state for at least 10 μs to ensure a proper reset initiation and recovery. 9 The self test time can extend when using external clock rates lower than 2000 Hz. 10 Power supply current transients can reach 100 mA during initial startup or reset recovery. Rev. PrA | Page 4 of 33
LOGIC INPUTS4 Input Voltage High, VIH 2.0 V Low, VIL 0.8 V RST Pulse Width 1 μs CS Wake-Up Pulse Width 20 μs Input Current Logic 1, IIH VIH = 3.3 V 10 μA Logic 0, IIL VIL = 0 V All Pins Except RST 10 μA RST Pin 0.33 mA Input Capacitance, CIN 10 pF DIGITAL OUTPUTS Output Voltage High, VOH ISOURCE = 0.5 mA 2.4 V Low, VOL ISINK = 2.0 mA 0.4 V FLASH MEMORY Endurance5 10000 Cycles Data Retention6 TJ = 85°C 20 Years FUNCTIONAL TIMES7 Time until data is available Power-On Start-Up Time 259 ms Reset Recovery Time8 GLOB_CMD, Bit 7 = 1 (see Table 113) 198 ms Factory Calibration Restore GLOB_CMD, Bit 1 = 1 (see Table 113) 143 ms Flash Memory Backup GLOB_CMD, Bit 3 = 1 (see Table 113) 72 ms Flash Memory Test Time GLOB_CMD, Bit 4 = 1 (see Table 113) 32 ms Self Test Time9 GLOB_CMD, Bit 2 = 1 (see Table 113) 20 ms CONVERSION RATE 2000 SPS Initial Clock Accuracy 3 % Sync Input Clock 1.9 2.1 kHz POWER SUPPLY, VDD Operating voltage range 3.0 3.6 V Power Supply Current10 Normal mode, VDD = 3.3 V 44 55 mA 1 The scale factors for each range are listed in Table 11. 2 This measurement is based on the deviation from a best fit linear model. 3 All specifications associated with the accelerometers relate to the full-scale range of ±8 g, unless otherwise noted. 4 The digital input/output signals use a 3.3 V system. 5 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −40°C, +25°C, +85°C, and +125°C. 6 The data retention specification assumes a junction temperature (TJ) of 85°C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ. 7 These times do not include thermal settling and internal filter response times, which may affect overall accuracy. 8 The RST line must be in a low state for at least 10 μs to ensure a proper reset initiation and recovery. 9 The self test time can extend when using external clock rates lower than 2000 Hz. 10 Power supply current transients can reach 100 mA during initial startup or reset recovery. Rev. PrA | Page 4 of 33
