Datasheet ADIS16467 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Precision MEMS IMU Module |
| Pages / Page | 34 / 6 — Preliminary Technical Data. ADIS16467. TIMING SPECIFICATIONS. Table 2. … |
| Revision | B |
| File Format / Size | PDF / 600 Kb |
| Document Language | English |
Preliminary Technical Data. ADIS16467. TIMING SPECIFICATIONS. Table 2. Normal Mode. Burst Read Mode. Parameter Description
Model Line for this Datasheet
Text Version of Document
Preliminary Technical Data ADIS16467 TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2. Normal Mode Burst Read Mode Parameter Description Min Typ Max Min1 Typ Max Unit
fSCLK Serial clock 0.1 2 0.1 1 MHz tSTALL Stall period between data 16 N/A μs tREADRATE Read rate 24 μs t Chip select to SCLK edge 200 200 ns CS tDAV DOUT valid after SCLK edge 25 25 ns tDSU DIN setup time before SCLK rising edge 25 25 ns tDHD DIN hold time after SCLK rising edge 50 50 ns tSCLKR, tSCLKF SCLK rise/fall times 5 12.5 5 12.5 ns tDR, tDF DOUT rise/fall times 5 12.5 5 12.5 ns tSFS CS high after SCLK edge 0 0 ns t1 Input sync positive pulse width; pulse sync mode, MSC_CTRL = 101 5 5 μs (binary, see Table 105) tSTDR Input sync to data ready valid transition Direct sync mode, MSC_CTRL = 001 (binary, see Table 105) 507 507 μs Pulse sync mode, MSC_CTRL = 101 (binary, see Table 105) 256 256 μs tNV Data invalid time 20 20 μs t2 Input sync period 500 500 μs 1 N/A means not applicable.
Timing Diagrams CS tSCLKR tSCLKF tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV tDR DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB tDSU tDHD tDF DIN
2
R/W A6 A5 A4 A3 A2 D2 D1 LSB
00 7- 543 1 Figure 2. SPI Timing and Sequence Diagram
READRATE STALL
003 37- 154 Figure 3. Stall Time and Data Rate Timing Diagram Rev. PrA | Page 5 of 33
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2. Normal Mode Burst Read Mode Parameter Description Min Typ Max Min1 Typ Max Unit
fSCLK Serial clock 0.1 2 0.1 1 MHz tSTALL Stall period between data 16 N/A μs tREADRATE Read rate 24 μs t Chip select to SCLK edge 200 200 ns CS tDAV DOUT valid after SCLK edge 25 25 ns tDSU DIN setup time before SCLK rising edge 25 25 ns tDHD DIN hold time after SCLK rising edge 50 50 ns tSCLKR, tSCLKF SCLK rise/fall times 5 12.5 5 12.5 ns tDR, tDF DOUT rise/fall times 5 12.5 5 12.5 ns tSFS CS high after SCLK edge 0 0 ns t1 Input sync positive pulse width; pulse sync mode, MSC_CTRL = 101 5 5 μs (binary, see Table 105) tSTDR Input sync to data ready valid transition Direct sync mode, MSC_CTRL = 001 (binary, see Table 105) 507 507 μs Pulse sync mode, MSC_CTRL = 101 (binary, see Table 105) 256 256 μs tNV Data invalid time 20 20 μs t2 Input sync period 500 500 μs 1 N/A means not applicable.
Timing Diagrams CS tSCLKR tSCLKF tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV tDR DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB tDSU tDHD tDF DIN
2
R/W A6 A5 A4 A3 A2 D2 D1 LSB
00 7- 543 1 Figure 2. SPI Timing and Sequence Diagram
READRATE STALL
003 37- 154 Figure 3. Stall Time and Data Rate Timing Diagram Rev. PrA | Page 5 of 33
