Datasheet ADIS16334 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Low Profile, Six Degrees of Freedom Inertial Sensor |
| Pages / Page | 21 / 6 — Data Sheet. ADIS16334. TIMING SPECIFICATIONS. Table 2. Normal Read. Burst … |
| Revision | D |
| File Format / Size | PDF / 496 Kb |
| Document Language | English |
Data Sheet. ADIS16334. TIMING SPECIFICATIONS. Table 2. Normal Read. Burst Read. Parameter Description. Min1 Ty. p Max Min. Max. Unit
Model Line for this Datasheet
Text Version of Document
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Data Sheet ADIS16334 TIMING SPECIFICATIONS
TA = 25°C, VCC = 5.0 V, unless otherwise noted.
Table 2. Normal Read Burst Read Parameter Description Min1 Ty p Max Min
1
Ty p Max Unit
fSCLK Serial clock 0.01 2.0 0.01 1.0 MHz tSTALL Stall period between data 9 N/A
2
μs tREADRATE Read rate 40 N/A2 μs t Chip select to SCLK edge 48.8 48.8 ns CS tDAV DOUT valid after SCLK edge 100 100 ns tDSU DIN setup time before SCLK rising edge 24.4 24.4 ns tDHD DIN hold time after SCLK rising edge 48.8 48.8 ns tSCLKR, tSCLKF SCLK rise/fall times 5 12.5 5 12.5 ns tDR, tDF DOUT rise/fall times 5 12.5 5 12.5 ns tSFS CS high after SCLK edge 5 5 ns t1 Input sync positive pulse width 5 5 μs tx Input sync low time 100 100 μs t2 Input sync to data ready output 600 600 μs t3 Input sync period 833 833 μs 1 Guaranteed by design and characterization, but not tested in production. 2 Does not apply to burst read.
TIMING DIAGRAMS CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
02 0 2- 36 09 Figure 2. SPI Timing and Sequence
tREADRATE tSTALL CS
3
SCLK
00 2- 36 09 Figure 3. Stall Time and Data Rate
t3 t2 t t 1 X SYNC CLOCK (DIO4)
04 0
DATA
2-
READY
36 09 Figure 4. Input Clock Timing Diagram Rev. B | Page 5 of 20 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Gyroscopes Accelerometers Data Sampling and Processing Calibration User Interface SPI Interface Basic Operation Reading Sensor Data Burst Read Function Memory Map Output Data Registers Gyroscopes Accelerometers Internal Temperature Measurements Device Configuration Dual Memory Structure Digital Processing Configuration Sample Rate Input Clock Configuration Digital Filtering Dynamic Range Optimizing Accuracy Automatic Bias Correction Manual Bias Correction Restoring Factory Calibration Point-of-Percussion/Linear-g Compensation System Tools Global Commands General-Purpose I/O Data Ready I/O Indicator Self-Test Memory Test Status Device Identification Flash Memory Management Alarms Static Alarm Use Dynamic Alarm Use Alarm Reporting Alarm Example Applications Information ADIS16334/PCBZ Installation Mounting Approaches Outline Dimensions Ordering Guide
Data Sheet ADIS16334 TIMING SPECIFICATIONS
TA = 25°C, VCC = 5.0 V, unless otherwise noted.
Table 2. Normal Read Burst Read Parameter Description Min1 Ty p Max Min
1
Ty p Max Unit
fSCLK Serial clock 0.01 2.0 0.01 1.0 MHz tSTALL Stall period between data 9 N/A
2
μs tREADRATE Read rate 40 N/A2 μs t Chip select to SCLK edge 48.8 48.8 ns CS tDAV DOUT valid after SCLK edge 100 100 ns tDSU DIN setup time before SCLK rising edge 24.4 24.4 ns tDHD DIN hold time after SCLK rising edge 48.8 48.8 ns tSCLKR, tSCLKF SCLK rise/fall times 5 12.5 5 12.5 ns tDR, tDF DOUT rise/fall times 5 12.5 5 12.5 ns tSFS CS high after SCLK edge 5 5 ns t1 Input sync positive pulse width 5 5 μs tx Input sync low time 100 100 μs t2 Input sync to data ready output 600 600 μs t3 Input sync period 833 833 μs 1 Guaranteed by design and characterization, but not tested in production. 2 Does not apply to burst read.
TIMING DIAGRAMS CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
02 0 2- 36 09 Figure 2. SPI Timing and Sequence
tREADRATE tSTALL CS
3
SCLK
00 2- 36 09 Figure 3. Stall Time and Data Rate
t3 t2 t t 1 X SYNC CLOCK (DIO4)
04 0
DATA
2-
READY
36 09 Figure 4. Input Clock Timing Diagram Rev. B | Page 5 of 20 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Gyroscopes Accelerometers Data Sampling and Processing Calibration User Interface SPI Interface Basic Operation Reading Sensor Data Burst Read Function Memory Map Output Data Registers Gyroscopes Accelerometers Internal Temperature Measurements Device Configuration Dual Memory Structure Digital Processing Configuration Sample Rate Input Clock Configuration Digital Filtering Dynamic Range Optimizing Accuracy Automatic Bias Correction Manual Bias Correction Restoring Factory Calibration Point-of-Percussion/Linear-g Compensation System Tools Global Commands General-Purpose I/O Data Ready I/O Indicator Self-Test Memory Test Status Device Identification Flash Memory Management Alarms Static Alarm Use Dynamic Alarm Use Alarm Reporting Alarm Example Applications Information ADIS16334/PCBZ Installation Mounting Approaches Outline Dimensions Ordering Guide
