Datasheet ADXRS810 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | High Performance, SPI Digital Output, Angular Rate Sensor |
| Pages / Page | 29 / 7 — ADXRS810. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. 16 … |
| File Format / Size | PDF / 677 Kb |
| Document Language | English |
ADXRS810. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. 16 SCLK. RSVD. 15 MOSI. 14 AVDD. 13 DV. TOP VIEW. MISO. (Not to Scale)
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ADXRS810 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DV 1 16 SCLK DD RSVD 2 15 MOSI RSVD 3 14 AVDD ADXRS810 CS 4 13 DV TOP VIEW SS MISO 5 (Not to Scale) 12 RSVD P 6 11 AV DD SS P 7 10 RSVD SS V 8 9 CP5
003
X
1034- 1 Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 DV Digital Regulated Voltage Output. See the Application Circuit section. DD 2, 3, 10, 12 RSVD Reserved for Analog Devices, Inc., Use Only. Connect to GND.1 4 CS Chip Select. 5 MISO Master In/Slave Out. 6 P Supply Voltage. DD 7 P Switching Regulator Ground (GND). SS 8 V High Voltage Switching Node. See the Application Circuit section. X 9 CP5 High Voltage Supply. See the Application Circuit section. 11 AV Analog Ground (GND). SS 13 DV Digital Signal Ground (GND). SS 14 AV Analog Regulated Voltage Output. See the Application Circuit section. DD 15 MOSI Master Out/Slave In. 16 SCLK SPI Clock. 1 The RSVD pins must be connected to PCB ground. For enhanced product diagnosis, make this connection through a trace and not directly through the package footprint. See the Suggested PCB Layout section for proper connection to the PCB. Rev. 0 | Page 6 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Applications Information Calibrated Performance Mechanical Considerations for Mounting Application Circuit ADXRS810 Signal Chain Timing SPI Communications Characteristics SPI Communication Protocol—Applications Device Data Latching Command/Response SPI Communication Protocol—Bit Definitions Command/Response Bit Descriptions ADXRS810 Fault Register Bit Definitions CHK Bit Assertion: Recommended Start-Up Routine SPI Rate Data Format ADXRS810 Memory Map Memory Register Definitions 0x00 RATE1, 0x01 RATE0 0x02 TEM1, 0x03 TEM0 0x04 LOCST1, 0x05 LOCST0 0x06 HICST1, 0x07 HICST0 0x08 QUAD1, 0x09 QUAD0 0x0A FAULT1, 0x0B FAULT0 0x0C PID1, 0x0D PID0 0x0E SN3, 0x0F SN2, 0x10 SN1, 0x11 SN0 Suggested PCB Layout Solder Profile Package Marking Codes Outline Dimensions Ordering Guide Automotive Products
ADXRS810 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DV 1 16 SCLK DD RSVD 2 15 MOSI RSVD 3 14 AVDD ADXRS810 CS 4 13 DV TOP VIEW SS MISO 5 (Not to Scale) 12 RSVD P 6 11 AV DD SS P 7 10 RSVD SS V 8 9 CP5
003
X
1034- 1 Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 DV Digital Regulated Voltage Output. See the Application Circuit section. DD 2, 3, 10, 12 RSVD Reserved for Analog Devices, Inc., Use Only. Connect to GND.1 4 CS Chip Select. 5 MISO Master In/Slave Out. 6 P Supply Voltage. DD 7 P Switching Regulator Ground (GND). SS 8 V High Voltage Switching Node. See the Application Circuit section. X 9 CP5 High Voltage Supply. See the Application Circuit section. 11 AV Analog Ground (GND). SS 13 DV Digital Signal Ground (GND). SS 14 AV Analog Regulated Voltage Output. See the Application Circuit section. DD 15 MOSI Master Out/Slave In. 16 SCLK SPI Clock. 1 The RSVD pins must be connected to PCB ground. For enhanced product diagnosis, make this connection through a trace and not directly through the package footprint. See the Suggested PCB Layout section for proper connection to the PCB. Rev. 0 | Page 6 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Applications Information Calibrated Performance Mechanical Considerations for Mounting Application Circuit ADXRS810 Signal Chain Timing SPI Communications Characteristics SPI Communication Protocol—Applications Device Data Latching Command/Response SPI Communication Protocol—Bit Definitions Command/Response Bit Descriptions ADXRS810 Fault Register Bit Definitions CHK Bit Assertion: Recommended Start-Up Routine SPI Rate Data Format ADXRS810 Memory Map Memory Register Definitions 0x00 RATE1, 0x01 RATE0 0x02 TEM1, 0x03 TEM0 0x04 LOCST1, 0x05 LOCST0 0x06 HICST1, 0x07 HICST0 0x08 QUAD1, 0x09 QUAD0 0x0A FAULT1, 0x0B FAULT0 0x0C PID1, 0x0D PID0 0x0E SN3, 0x0F SN2, 0x10 SN1, 0x11 SN0 Suggested PCB Layout Solder Profile Package Marking Codes Outline Dimensions Ordering Guide Automotive Products
