Datasheet ADXRS453 (Analog Devices) - 3

ManufacturerAnalog Devices
DescriptionHigh Performance, Digital Output Gyroscope
Pages / Page33 / 3 — ADXRS453. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 12/11—Rev. A …
RevisionB
File Format / SizePDF / 833 Kb
Document LanguageEnglish

ADXRS453. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 12/11—Rev. A to Rev. B. 6/11—Rev. 0 to Rev. A

ADXRS453 Data Sheet TABLE OF CONTENTS REVISION HISTORY 12/11—Rev A to Rev B 6/11—Rev 0 to Rev A

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ADXRS453 Data Sheet TABLE OF CONTENTS
Features .. 1  ADXRS453 Signal Chain Timing ... 13  Applications ... 1  SPI Communication Protocol ... 14  General Description ... 1  Command/Response ... 14  Functional Block Diagram .. 1  Device Data Latching ... 15  Revision History ... 2  SPI Timing Characteristics ... 16  Specifications ... 3  Command/Response Bit Definitions ... 17  Absolute Maximum Ratings .. 4  Fault Register Bit Definitions ... 18  Thermal Resistance .. 4  Recommended Start-Up Sequence with CHK Bit Assertion .. 20  Rate Sensitive Axis ... 4  Rate Data Format .. 21  ESD Caution .. 4  Memory Map and Registers .. 22  Pin Configurations and Function Descriptions ... 5  Memory Map .. 22  Typical Performance Characteristics ... 7  Memory Register Definitions ... 23  Theory of Operation .. 9  Package Orientation and Layout Information .. 25  Continuous Self-Test .. 9  Solder Profile... 26  Mechanical Performance ... 10  Package Marking Codes .. 27  Noise Performance ... 11  Outline Dimensions ... 28  Applications Information .. 12  Ordering Guide .. 29  Calibrated Performance ... 12  Mechanical Considerations for Mounting .. 12  Application Circuits ... 12 
REVISION HISTORY 12/11—Rev. A to Rev. B
Changes to Features Section.. 1 Changes to Rate Sensitive Axis Section ... 4 Deleted Endnote 1, Table 3 .. 4 Deleted Figure 5; Renumbered Sequentially ... 6 Changes to Figure 4 .. 6 Changes to Figure 32 .. 25 Deleted Figure 36 .. 26
6/11—Rev. 0 to Rev. A
Changes to Bit 30 and Bit 31 in Table 9 ... 14 Updated Outline Dimensions ... 29 Changes to Ordering Guide .. 30
1/11—Revision 0: Initial Version
Rev. B | Page 2 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Mechanical Performance Noise Performance Applications Information Calibrated Performance Mechanical Considerations for Mounting Application Circuits ADXRS453 Signal Chain Timing SPI Communication Protocol Command/Response Device Data Latching SPI Timing Characteristics Command/Response Bit Definitions SQ2 to SQ0 Bits SM2 to SM0 Bits A8 to A0 Bits D15 to D0 Bits P Bit SPI Bit RE Bit DU Bit ST1 and ST0 Bits P0 Bit P1 Bit Fault Register Bit Definitions Fail Bit AMP Bit OV Bit UV Bit PLL Bit Q Bit NVM Bit POR Bit PWR Bit CST Bit CHK Bit Recommended Start-Up Sequence with CHK Bit Assertion Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate (RATEx) Registers Temperature (TEMx) Registers Low CST (LOCSTx) Registers High CST (HICSTx) Registers Quad Memory (QUADx) Registers Fault (FAULTx) Registers Part ID (PIDx) Registers Serial Number (SNx) Registers Package Orientation and Layout Information Solder Profile Package Marking Codes Outline Dimensions Ordering Guide