Datasheet ADXRS453 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | High Performance, Digital Output Gyroscope |
| Pages / Page | 33 / 6 — Data Sheet. ADXRS453. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. 16 … |
| Revision | B |
| File Format / Size | PDF / 833 Kb |
| Document Language | English |
Data Sheet. ADXRS453. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. 16 SCLK. RSVD 2. 15 MOSI. RSVD 3. 14 AVDD. CS 4. 13 DV. TOP VIEW
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Data Sheet ADXRS453 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DV 1 16 SCLK DD RSVD 2 15 MOSI RSVD 3 14 AVDD ADXRS453 CS 4 13 DV TOP VIEW SS (Not to Scale) MISO 5 12 RSVD P 6 11 DD AVSS P 7 10 SS RSVD
3
V 8 9 X CP5
00 5- 15 09 Figure 3. Pin Configuration, 16-Lead SOIC_CAV
Table 4. Pin Function Descriptions, 16-Lead SOIC_CAV Pin No. Mnemonic Description
1 DVDD Digital Regulated Voltage. See Figure 25 for the application circuit diagram. 2 RSVD Reserved. This pin must be connected to DVSS. 3 RSVD Reserved. This pin must be connected to DVSS. 4 CS Chip Select. 5 MISO Master In/Slave Out. 6 PDD Supply Voltage. 7 PSS Switching Regulator Ground. 8 VX High Voltage Switching Node. See Figure 25 for the application circuit diagram. 9 CP5 High Voltage Supply. See Figure 25 for the application circuit diagram. 10 RSVD Reserved. This pin must be connected to DVSS. 11 AVSS Analog Ground. 12 RSVD Reserved. This pin must be connected to DVSS. 13 DVSS Digital Signal Ground. 14 AVDD Analog Regulated Voltage. See Figure 25 for the application circuit diagram. 15 MOSI Master Out/Slave In. 16 SCLK SPI Clock. Rev. B | Page 5 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Mechanical Performance Noise Performance Applications Information Calibrated Performance Mechanical Considerations for Mounting Application Circuits ADXRS453 Signal Chain Timing SPI Communication Protocol Command/Response Device Data Latching SPI Timing Characteristics Command/Response Bit Definitions SQ2 to SQ0 Bits SM2 to SM0 Bits A8 to A0 Bits D15 to D0 Bits P Bit SPI Bit RE Bit DU Bit ST1 and ST0 Bits P0 Bit P1 Bit Fault Register Bit Definitions Fail Bit AMP Bit OV Bit UV Bit PLL Bit Q Bit NVM Bit POR Bit PWR Bit CST Bit CHK Bit Recommended Start-Up Sequence with CHK Bit Assertion Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate (RATEx) Registers Temperature (TEMx) Registers Low CST (LOCSTx) Registers High CST (HICSTx) Registers Quad Memory (QUADx) Registers Fault (FAULTx) Registers Part ID (PIDx) Registers Serial Number (SNx) Registers Package Orientation and Layout Information Solder Profile Package Marking Codes Outline Dimensions Ordering Guide
Data Sheet ADXRS453 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DV 1 16 SCLK DD RSVD 2 15 MOSI RSVD 3 14 AVDD ADXRS453 CS 4 13 DV TOP VIEW SS (Not to Scale) MISO 5 12 RSVD P 6 11 DD AVSS P 7 10 SS RSVD
3
V 8 9 X CP5
00 5- 15 09 Figure 3. Pin Configuration, 16-Lead SOIC_CAV
Table 4. Pin Function Descriptions, 16-Lead SOIC_CAV Pin No. Mnemonic Description
1 DVDD Digital Regulated Voltage. See Figure 25 for the application circuit diagram. 2 RSVD Reserved. This pin must be connected to DVSS. 3 RSVD Reserved. This pin must be connected to DVSS. 4 CS Chip Select. 5 MISO Master In/Slave Out. 6 PDD Supply Voltage. 7 PSS Switching Regulator Ground. 8 VX High Voltage Switching Node. See Figure 25 for the application circuit diagram. 9 CP5 High Voltage Supply. See Figure 25 for the application circuit diagram. 10 RSVD Reserved. This pin must be connected to DVSS. 11 AVSS Analog Ground. 12 RSVD Reserved. This pin must be connected to DVSS. 13 DVSS Digital Signal Ground. 14 AVDD Analog Regulated Voltage. See Figure 25 for the application circuit diagram. 15 MOSI Master Out/Slave In. 16 SCLK SPI Clock. Rev. B | Page 5 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Mechanical Performance Noise Performance Applications Information Calibrated Performance Mechanical Considerations for Mounting Application Circuits ADXRS453 Signal Chain Timing SPI Communication Protocol Command/Response Device Data Latching SPI Timing Characteristics Command/Response Bit Definitions SQ2 to SQ0 Bits SM2 to SM0 Bits A8 to A0 Bits D15 to D0 Bits P Bit SPI Bit RE Bit DU Bit ST1 and ST0 Bits P0 Bit P1 Bit Fault Register Bit Definitions Fail Bit AMP Bit OV Bit UV Bit PLL Bit Q Bit NVM Bit POR Bit PWR Bit CST Bit CHK Bit Recommended Start-Up Sequence with CHK Bit Assertion Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate (RATEx) Registers Temperature (TEMx) Registers Low CST (LOCSTx) Registers High CST (HICSTx) Registers Quad Memory (QUADx) Registers Fault (FAULTx) Registers Part ID (PIDx) Registers Serial Number (SNx) Registers Package Orientation and Layout Information Solder Profile Package Marking Codes Outline Dimensions Ordering Guide
