Datasheet ADXRS453 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | High Performance, Digital Output Gyroscope |
| Pages / Page | 33 / 7 — ADXRS453. Data Sheet. SVD. 12 11 10. TOP VIEW. (Not to Scale). NOTES |
| Revision | B |
| File Format / Size | PDF / 833 Kb |
| Document Language | English |
ADXRS453. Data Sheet. SVD. 12 11 10. TOP VIEW. (Not to Scale). NOTES
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ADXRS453 Data Sheet SI SS DD SS X SVD P P MO DV CS V R 14 13 12 11 10 9 8 1 2 3 4 5 6 7 5 SS K DD SO DD L AV CP AV MI DV SVD SC R TOP VIEW (Not to Scale) NOTES 1. THE PACKAGE HAS TERMINALS ON TWO FACES. HOWEVER, THE TERMINALS ON THE BACK ARE FOR INTERNAL EVALUATION ONLY AND SHOULD NOT BE USED IN THE END APPLICATION. THE TERMINALS ON THE BOTTOM OF THE PACKAGE INCORPORATE METALLIZATION BUMPS THAT ENSURE A MINIMUM SOLDER THICKNESS FOR IMPROVED SOLDER JOINT RELIABILITY. THESE BUMPS ARE NOT PRESENT ON THE BACK TERMINALS AND, THEREFORE, POOR SOLDER JOINT RELIABILITY CAN BE ENCOUNTERED IF THE BACK TERMINALS ARE USED
04 0
IN THE END APPLICATION. FOR THE OUTLINE DIMENSIONS OF THIS PACKAGE,
55-
SEE FIGURE 38.
091 Figure 4. Pin Configuration, 14-Terminal LCC_V
Table 5. Pin Function Descriptions, 14-Terminal LCC_V Pin No. Mnemonic Description
1 AVSS Analog Ground. 2 AVDD Analog Regulated Voltage. See Figure 26 for the application circuit diagram. 3 MISO Master In/Slave Out. 4 DVDD Digital Regulated Voltage. See Figure 26 for the application circuit diagram. 5 SCLK SPI Clock. 6 CP5 High Voltage Supply. See Figure 26 for the application circuit diagram. 7 RSVD Reserved. This pin must be connected to DVSS. 8 RSVD Reserved. This pin must be connected to DVSS. 9 VX High Voltage Switching Node. See Figure 26 for the application circuit diagram. 10 CS Chip Select. 11 DVSS Digital Signal Ground. 12 MOSI Master Out/Slave In. 13 PSS Switching Regulator Ground. 14 PDD Supply Voltage. Rev. B | Page 6 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Mechanical Performance Noise Performance Applications Information Calibrated Performance Mechanical Considerations for Mounting Application Circuits ADXRS453 Signal Chain Timing SPI Communication Protocol Command/Response Device Data Latching SPI Timing Characteristics Command/Response Bit Definitions SQ2 to SQ0 Bits SM2 to SM0 Bits A8 to A0 Bits D15 to D0 Bits P Bit SPI Bit RE Bit DU Bit ST1 and ST0 Bits P0 Bit P1 Bit Fault Register Bit Definitions Fail Bit AMP Bit OV Bit UV Bit PLL Bit Q Bit NVM Bit POR Bit PWR Bit CST Bit CHK Bit Recommended Start-Up Sequence with CHK Bit Assertion Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate (RATEx) Registers Temperature (TEMx) Registers Low CST (LOCSTx) Registers High CST (HICSTx) Registers Quad Memory (QUADx) Registers Fault (FAULTx) Registers Part ID (PIDx) Registers Serial Number (SNx) Registers Package Orientation and Layout Information Solder Profile Package Marking Codes Outline Dimensions Ordering Guide
ADXRS453 Data Sheet SI SS DD SS X SVD P P MO DV CS V R 14 13 12 11 10 9 8 1 2 3 4 5 6 7 5 SS K DD SO DD L AV CP AV MI DV SVD SC R TOP VIEW (Not to Scale) NOTES 1. THE PACKAGE HAS TERMINALS ON TWO FACES. HOWEVER, THE TERMINALS ON THE BACK ARE FOR INTERNAL EVALUATION ONLY AND SHOULD NOT BE USED IN THE END APPLICATION. THE TERMINALS ON THE BOTTOM OF THE PACKAGE INCORPORATE METALLIZATION BUMPS THAT ENSURE A MINIMUM SOLDER THICKNESS FOR IMPROVED SOLDER JOINT RELIABILITY. THESE BUMPS ARE NOT PRESENT ON THE BACK TERMINALS AND, THEREFORE, POOR SOLDER JOINT RELIABILITY CAN BE ENCOUNTERED IF THE BACK TERMINALS ARE USED
04 0
IN THE END APPLICATION. FOR THE OUTLINE DIMENSIONS OF THIS PACKAGE,
55-
SEE FIGURE 38.
091 Figure 4. Pin Configuration, 14-Terminal LCC_V
Table 5. Pin Function Descriptions, 14-Terminal LCC_V Pin No. Mnemonic Description
1 AVSS Analog Ground. 2 AVDD Analog Regulated Voltage. See Figure 26 for the application circuit diagram. 3 MISO Master In/Slave Out. 4 DVDD Digital Regulated Voltage. See Figure 26 for the application circuit diagram. 5 SCLK SPI Clock. 6 CP5 High Voltage Supply. See Figure 26 for the application circuit diagram. 7 RSVD Reserved. This pin must be connected to DVSS. 8 RSVD Reserved. This pin must be connected to DVSS. 9 VX High Voltage Switching Node. See Figure 26 for the application circuit diagram. 10 CS Chip Select. 11 DVSS Digital Signal Ground. 12 MOSI Master Out/Slave In. 13 PSS Switching Regulator Ground. 14 PDD Supply Voltage. Rev. B | Page 6 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Mechanical Performance Noise Performance Applications Information Calibrated Performance Mechanical Considerations for Mounting Application Circuits ADXRS453 Signal Chain Timing SPI Communication Protocol Command/Response Device Data Latching SPI Timing Characteristics Command/Response Bit Definitions SQ2 to SQ0 Bits SM2 to SM0 Bits A8 to A0 Bits D15 to D0 Bits P Bit SPI Bit RE Bit DU Bit ST1 and ST0 Bits P0 Bit P1 Bit Fault Register Bit Definitions Fail Bit AMP Bit OV Bit UV Bit PLL Bit Q Bit NVM Bit POR Bit PWR Bit CST Bit CHK Bit Recommended Start-Up Sequence with CHK Bit Assertion Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate (RATEx) Registers Temperature (TEMx) Registers Low CST (LOCSTx) Registers High CST (HICSTx) Registers Quad Memory (QUADx) Registers Fault (FAULTx) Registers Part ID (PIDx) Registers Serial Number (SNx) Registers Package Orientation and Layout Information Solder Profile Package Marking Codes Outline Dimensions Ordering Guide
