Datasheet ADIS16260, ADIS16265 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Programmable Digital Gyroscope Sensor |
| Pages / Page | 20 / 5 — Data Sheet. ADIS16260/ADIS16265. TIMING SPECIFICATIONS. Table 2. Normal … |
| Revision | F |
| File Format / Size | PDF / 405 Kb |
| Document Language | English |
Data Sheet. ADIS16260/ADIS16265. TIMING SPECIFICATIONS. Table 2. Normal Mode. Low Power Mode
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Data Sheet ADIS16260/ADIS16265 TIMING SPECIFICATIONS
TA = −40°C to +85°C, VCC = 5.0 V, unless otherwise noted.
Table 2. Normal Mode Low Power Mode (SMPL_PRD[7:0] ≤ 0x07, fS ≥ 64 Hz) (SMPL_PRD[7:0] ≥ 0x08, fS ≤ 56.9 Hz) Parameter Description Min1 Typ Max1 Min1 Typ Max1 Unit
fSCLK Serial clock 0.01 2.5 0.01 1.0 MHz tDATARATE Data rate period 32 42 µs tSTALL Stall period between data 9 12 µs t Chip select to clock edge 48.8 48.8 ns CS tDAV Data output valid after SCLK falling 100 100 ns edge2 tDSU Data input setup time before SCLK 24.4 24.4 ns rising edge tDHD Data input hold time after SCLK 48.8 48.8 ns rising edge tDF Data output fall time 5 12.5 5 12.5 ns tDR Data output rise time 5 12.5 5 12.5 ns tSFS CS high after SCLK edge3 5 5 ns 1 Guaranteed by design; not production tested. 2 The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The rest of the DOUT bits are clocked after the falling edge of SCLK and are governed by this specification. 3 This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state.
Timing Diagrams tDATARATE CS SCLK
002
tSTALL
08246- Figure 2. SPI Chip Select Timing
CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT * MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A5 A4 A3 A2 D2 D1 LSB
003
*NOT DEFINED
08246- Figure 3. SPI Timing (Using SPI Settings Typically Identified as CPOL = 1, CPHA = 1) Rev. E | Page 5 of 20 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Sensing Element Data Sampling and Processing User Interface SPI Interface User Registers Basic Operation SPI Write Commands SPI Read Commands Memory Map Processing Sensor Data Operational Controls Internal Sample Rate Sensor Bandwidth Digital Filtering Dynamic Range Calibration Global Commands Power Management Input/Output Functions General-Purpose I/O Data Ready I/O Indicator Auxiliary DAC Diagnostics Self-Test Memory Test Status Alarm Registers Product Identification Applications Information Assembly Bias Optimization Interface Printed Circuit Board (PCB) Outline Dimensions Ordering Guide
Data Sheet ADIS16260/ADIS16265 TIMING SPECIFICATIONS
TA = −40°C to +85°C, VCC = 5.0 V, unless otherwise noted.
Table 2. Normal Mode Low Power Mode (SMPL_PRD[7:0] ≤ 0x07, fS ≥ 64 Hz) (SMPL_PRD[7:0] ≥ 0x08, fS ≤ 56.9 Hz) Parameter Description Min1 Typ Max1 Min1 Typ Max1 Unit
fSCLK Serial clock 0.01 2.5 0.01 1.0 MHz tDATARATE Data rate period 32 42 µs tSTALL Stall period between data 9 12 µs t Chip select to clock edge 48.8 48.8 ns CS tDAV Data output valid after SCLK falling 100 100 ns edge2 tDSU Data input setup time before SCLK 24.4 24.4 ns rising edge tDHD Data input hold time after SCLK 48.8 48.8 ns rising edge tDF Data output fall time 5 12.5 5 12.5 ns tDR Data output rise time 5 12.5 5 12.5 ns tSFS CS high after SCLK edge3 5 5 ns 1 Guaranteed by design; not production tested. 2 The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The rest of the DOUT bits are clocked after the falling edge of SCLK and are governed by this specification. 3 This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state.
Timing Diagrams tDATARATE CS SCLK
002
tSTALL
08246- Figure 2. SPI Chip Select Timing
CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT * MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A5 A4 A3 A2 D2 D1 LSB
003
*NOT DEFINED
08246- Figure 3. SPI Timing (Using SPI Settings Typically Identified as CPOL = 1, CPHA = 1) Rev. E | Page 5 of 20 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Sensing Element Data Sampling and Processing User Interface SPI Interface User Registers Basic Operation SPI Write Commands SPI Read Commands Memory Map Processing Sensor Data Operational Controls Internal Sample Rate Sensor Bandwidth Digital Filtering Dynamic Range Calibration Global Commands Power Management Input/Output Functions General-Purpose I/O Data Ready I/O Indicator Auxiliary DAC Diagnostics Self-Test Memory Test Status Alarm Registers Product Identification Applications Information Assembly Bias Optimization Interface Printed Circuit Board (PCB) Outline Dimensions Ordering Guide
