Datasheet KSZ8775CLX (Microchip) - 2
| Manufacturer | Microchip |
| Description | Integrated 5–Port 10/100 Managed Ethernet Switch with Port 4 RMII and Port 5 RGMII/MII/ RMII Interfaces |
| Pages / Page | 132 / 2 — KSZ8775CLX. -1 kb entry forwarding table with 64 kb frame. buffer. -Four … |
| File Format / Size | PDF / 2.3 Mb |
| Document Language | English |
KSZ8775CLX. -1 kb entry forwarding table with 64 kb frame. buffer. -Four priority queues with dynamic packet
Model Line for this Datasheet
Text Version of Document
KSZ8775CLX
-1 kb entry forwarding table with 64 kb frame
buffer
-Four priority queues with dynamic packet
mapping for IEEE 802.1p, IPv4 ToS (DIFFSERV), IPv6 traffic class, etc.
-Supports Wake-on-LAN (WoL) using AMD’s
Magic Packet™
-VLAN and address filtering
-Supports 802.1x port-based security, authentication, and MAC-based authentication via
access control lists (ACL)
-Provides port-based and rule-based ACLs to
support Layer 2 MAC SA/DA address, Layer
3 IP address and IP mask, Layer 4 TCP/UDP
port number, IP protocol, TCP flag, and compensation for the port security filtering
-Ingress and egress rate limit based on bit per
second (bps) and packet-based rate limiting
(pps)
• Configuration Registers Access
-High speed (4-wire, up to 50 MHz) interface
(SPI) to access all internal registers
-MII management interface (MIIM, MDC/
MDIO 2-wire) to access all PHY registers per
clause 22.2.4.5 of the IEEE 802.3 specification
-I/O pin strapping facility to set certain register
bits from I/O pins during reset time
-Control registers configurable on-the-fly
• Power and Power Management
-Full-chip software power down (all registers
value are not saved and strap-in value will restrap after release of the power down)
-Per-port software power down
-Energy detect power down (EDPD), which
disables the PHY transceiver when cables
are removed
-Supports IEEE P802.3az Energy Efficient
Ethernet to reduce power consumption in
transceivers in LPI state even though cables
are not removed
-Dynamic clock tree control to reduce clocking
in areas not in use
-Low power consumption without extra power
consumption on transformers
-Voltages: Using external LDO power supplies.
-Analog VDDAT 3.3V
-VDDIO support
-s 3.3V, 2.5V, and 1.8V
-Low 1.2V voltage for analog and digital core
power
-Wake-on-LAN support with configurable
packet control
• Additional Features 2015 Microchip Technology Inc. • • • • -Single 25 MHz +50 ppm reference clock
requirement
Comprehensive programmable two LED indicator
support for link, activity, full/half-duplex, and 10/
100 speed
Packaging and Environmental
-Commercial temperature range: 0°C to
+70°C
Industrial temperature range: –40°C to +85°C
-Package available in an 80-pin lead free
(RoHS) LQFP form factor
-Supports HBM ESD rating of 5 kV
-0.065 µm CMOS technology for lower power
consumption
Applications
-Set-Top Boxes
-Networked Printers and Servers
-Test Instrumentation
-LAN on Motherboard
-Embedded Telecom Applications
-Video Record/Playback Systems
-Cable Modems/Routers
-DSL Modems/Routers
-Digital Video Recorders
-IP and Video Phones
-Wireless Access Points
-Digital Televisions
-Digital Media Adapters/Servers
-Gaming Consoles DS00002129C-page 2
-1 kb entry forwarding table with 64 kb frame
buffer
-Four priority queues with dynamic packet
mapping for IEEE 802.1p, IPv4 ToS (DIFFSERV), IPv6 traffic class, etc.
-Supports Wake-on-LAN (WoL) using AMD’s
Magic Packet™
-VLAN and address filtering
-Supports 802.1x port-based security, authentication, and MAC-based authentication via
access control lists (ACL)
-Provides port-based and rule-based ACLs to
support Layer 2 MAC SA/DA address, Layer
3 IP address and IP mask, Layer 4 TCP/UDP
port number, IP protocol, TCP flag, and compensation for the port security filtering
-Ingress and egress rate limit based on bit per
second (bps) and packet-based rate limiting
(pps)
• Configuration Registers Access
-High speed (4-wire, up to 50 MHz) interface
(SPI) to access all internal registers
-MII management interface (MIIM, MDC/
MDIO 2-wire) to access all PHY registers per
clause 22.2.4.5 of the IEEE 802.3 specification
-I/O pin strapping facility to set certain register
bits from I/O pins during reset time
-Control registers configurable on-the-fly
• Power and Power Management
-Full-chip software power down (all registers
value are not saved and strap-in value will restrap after release of the power down)
-Per-port software power down
-Energy detect power down (EDPD), which
disables the PHY transceiver when cables
are removed
-Supports IEEE P802.3az Energy Efficient
Ethernet to reduce power consumption in
transceivers in LPI state even though cables
are not removed
-Dynamic clock tree control to reduce clocking
in areas not in use
-Low power consumption without extra power
consumption on transformers
-Voltages: Using external LDO power supplies.
-Analog VDDAT 3.3V
-VDDIO support
-s 3.3V, 2.5V, and 1.8V
-Low 1.2V voltage for analog and digital core
power
-Wake-on-LAN support with configurable
packet control
• Additional Features 2015 Microchip Technology Inc. • • • • -Single 25 MHz +50 ppm reference clock
requirement
Comprehensive programmable two LED indicator
support for link, activity, full/half-duplex, and 10/
100 speed
Packaging and Environmental
-Commercial temperature range: 0°C to
+70°C
Industrial temperature range: –40°C to +85°C
-Package available in an 80-pin lead free
(RoHS) LQFP form factor
-Supports HBM ESD rating of 5 kV
-0.065 µm CMOS technology for lower power
consumption
Applications
-Set-Top Boxes
-Networked Printers and Servers
-Test Instrumentation
-LAN on Motherboard
-Embedded Telecom Applications
-Video Record/Playback Systems
-Cable Modems/Routers
-DSL Modems/Routers
-Digital Video Recorders
-IP and Video Phones
-Wireless Access Points
-Digital Televisions
-Digital Media Adapters/Servers
-Gaming Consoles DS00002129C-page 2
