Datasheet KSZ8873MLL, KSZ8873FLL, KSZ8873RLL (Microchip) - 5
| Manufacturer | Microchip |
| Description | Integrated 3-Port 10/100 Managed Switch with PHYs |
| Pages / Page | 95 / 5 — KSZ8873MLL/FLL/RLL. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE 2-1:. … |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
KSZ8873MLL/FLL/RLL. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE 2-1:. 64-PIN 10 MM X 10 MM LQFP ASSIGNMENT, (TOP VIEW)
Model Line for this Datasheet
Text Version of Document
KSZ8873MLL/FLL/RLL 2.0 PIN DESCRIPTION AND CONFIGURATION FIGURE 2-1: 64-PIN 10 MM X 10 MM LQFP ASSIGNMENT, (TOP VIEW)
VDDA_1.8 FXSD1 RSTN P2LED0 P2LED1 P1LED0 P1LED1 NC VDDCO GND VDDIO NC NC P3SPD P1FFC VDDC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RXM1 1 48 GND RXP1 2 47 P1DPX AGND 3 46 P1SPD TXM1 4 45 P1ANEN TXP1 5 44 NC VDDA_3.3 6 43 SDA_MDIO AGND 7 42 SCL_MDC ISET 8 41 INTRN VDDA_1.8 9 40 SPISN RXM2 10 39 SPIQ RXP2 11 38 VDDC AGND 12 37 GND TXM2 13 36 SMRXC3 TXP2 14 35 SCOL3 FXSD2 15 34 SCRS3 PWRDN 16 33 SMRXD30 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 X1 X2 GND GND VDDIO SMTXEN3 SMTXD32 SMTXD31 SMTXD30 SMRXDV3 SMRXD32 SMRXD31 SMTXC3/REFCLKI_3 SMTXER3/MII_LINK_3 SMRXD33/REFCLKO_3 SMTXD33/EN_REFCLKO_3 2017 Microchip Technology Inc. DS00002348A-page 5 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Input Timing 7.7 SPI Output Timing 7.8 Auto-Negotiation Timing 7.9 MDC/MDIO Timing 7.10 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service
VDDA_1.8 FXSD1 RSTN P2LED0 P2LED1 P1LED0 P1LED1 NC VDDCO GND VDDIO NC NC P3SPD P1FFC VDDC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RXM1 1 48 GND RXP1 2 47 P1DPX AGND 3 46 P1SPD TXM1 4 45 P1ANEN TXP1 5 44 NC VDDA_3.3 6 43 SDA_MDIO AGND 7 42 SCL_MDC ISET 8 41 INTRN VDDA_1.8 9 40 SPISN RXM2 10 39 SPIQ RXP2 11 38 VDDC AGND 12 37 GND TXM2 13 36 SMRXC3 TXP2 14 35 SCOL3 FXSD2 15 34 SCRS3 PWRDN 16 33 SMRXD30 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 X1 X2 GND GND VDDIO SMTXEN3 SMTXD32 SMTXD31 SMTXD30 SMRXDV3 SMRXD32 SMRXD31 SMTXC3/REFCLKI_3 SMTXER3/MII_LINK_3 SMRXD33/REFCLKO_3 SMTXD33/EN_REFCLKO_3 2017 Microchip Technology Inc. DS00002348A-page 5 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Input Timing 7.7 SPI Output Timing 7.8 Auto-Negotiation Timing 7.9 MDC/MDIO Timing 7.10 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service
