Datasheet KSZ8873MLL, KSZ8873FLL, KSZ8873RLL (Microchip) - 6
| Manufacturer | Microchip |
| Description | Integrated 3-Port 10/100 Managed Switch with PHYs |
| Pages / Page | 95 / 6 — KSZ8873MLL/FLL/RLL. TABLE 2-1:. SIGNALS. Type. Pin. Note. Description. … |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
KSZ8873MLL/FLL/RLL. TABLE 2-1:. SIGNALS. Type. Pin. Note. Description. Number. Name. 2-1. Strap option:
Model Line for this Datasheet
Text Version of Document
link to page 11 link to page 11
KSZ8873MLL/FLL/RLL TABLE 2-1: SIGNALS Type Pin Pin Note Description Number Name 2-1
1 RXM1 I/O Physical receive or transmit signal (– differential) 2 RXP1 I/O Physical receive or transmit signal (+ differential) 3 AGND GND Analog ground 4 TXM1 I/O Physical transmit or receive signal (– differential) 5 TXP1 I/O Physical transmit or receive signal (+ differential) 6 VDDA_3.3 P 3.3V analog VDD 7 AGND GND Analog ground Set physical transmit output current. 8 ISET O Pull-down this pin with an 11.8kΩ 1% resistor to ground. 9 VDDA_1.8 P 1.8V analog core power input from VDDCO (pin 56). 10 RXM2 I/O Physical receive or transmit signal (– differential) 11 RXP2 I/O Physical receive or transmit signal (+ differential) 12 AGND GND Analog ground 13 TXM2 I/O Physical transmit or receive signal (– differential) 14 TXP2 I/O Physical transmit or receive signal (+ differential) MLL/RLL: connect to analog ground by pull-down resistor. 15 FXSD2 I FLL: Fiber signal detect/factory test pin 16 PWRDN Ipu Chip power down input (active-low) 17 X1 I 25 MHz or 50 MHz crystal/oscillator clock connections. Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a NC. 18 X2 O Note: Clock is ±50 ppm for both crystal and oscillator, the clock should be applied to X1 pin before reset voltage goes high. 19 SMTXEN3 Ipu Switch MII transmit enable MLL/FLL: Switch MII transmit data bit 3 RLL: 20 SMTXD33/ Ipu/I
Strap option:
RMII mode Clock selection EN_REFCLKO_3 PU = Enable REFCLKO_3 output PD = Disable REFCLKO_3 output SMTXD32/ MLL/FLL: Switch MII transmit data bit 2 21 Ipu NC RLL: No connection 22 SMTXD31 Ipu Switch MII/RMII transmit data bit 1 23 SMTXD30 Ipu Switch MII/RMII transmit data bit 0 24 GND GND Digital ground 3.3V, 2.5V, or 1.8V digital V 25 VDDIO P DD input power supply for IO with well decoupling capacitors. DS00002348A-page 6 2017 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Input Timing 7.7 SPI Output Timing 7.8 Auto-Negotiation Timing 7.9 MDC/MDIO Timing 7.10 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service
KSZ8873MLL/FLL/RLL TABLE 2-1: SIGNALS Type Pin Pin Note Description Number Name 2-1
1 RXM1 I/O Physical receive or transmit signal (– differential) 2 RXP1 I/O Physical receive or transmit signal (+ differential) 3 AGND GND Analog ground 4 TXM1 I/O Physical transmit or receive signal (– differential) 5 TXP1 I/O Physical transmit or receive signal (+ differential) 6 VDDA_3.3 P 3.3V analog VDD 7 AGND GND Analog ground Set physical transmit output current. 8 ISET O Pull-down this pin with an 11.8kΩ 1% resistor to ground. 9 VDDA_1.8 P 1.8V analog core power input from VDDCO (pin 56). 10 RXM2 I/O Physical receive or transmit signal (– differential) 11 RXP2 I/O Physical receive or transmit signal (+ differential) 12 AGND GND Analog ground 13 TXM2 I/O Physical transmit or receive signal (– differential) 14 TXP2 I/O Physical transmit or receive signal (+ differential) MLL/RLL: connect to analog ground by pull-down resistor. 15 FXSD2 I FLL: Fiber signal detect/factory test pin 16 PWRDN Ipu Chip power down input (active-low) 17 X1 I 25 MHz or 50 MHz crystal/oscillator clock connections. Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a NC. 18 X2 O Note: Clock is ±50 ppm for both crystal and oscillator, the clock should be applied to X1 pin before reset voltage goes high. 19 SMTXEN3 Ipu Switch MII transmit enable MLL/FLL: Switch MII transmit data bit 3 RLL: 20 SMTXD33/ Ipu/I
Strap option:
RMII mode Clock selection EN_REFCLKO_3 PU = Enable REFCLKO_3 output PD = Disable REFCLKO_3 output SMTXD32/ MLL/FLL: Switch MII transmit data bit 2 21 Ipu NC RLL: No connection 22 SMTXD31 Ipu Switch MII/RMII transmit data bit 1 23 SMTXD30 Ipu Switch MII/RMII transmit data bit 0 24 GND GND Digital ground 3.3V, 2.5V, or 1.8V digital V 25 VDDIO P DD input power supply for IO with well decoupling capacitors. DS00002348A-page 6 2017 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Input Timing 7.7 SPI Output Timing 7.8 Auto-Negotiation Timing 7.9 MDC/MDIO Timing 7.10 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service
