Datasheet KSZ8873MLL, KSZ8873FLL, KSZ8873RLL (Microchip) - 7
| Manufacturer | Microchip |
| Description | Integrated 3-Port 10/100 Managed Switch with PHYs |
| Pages / Page | 95 / 7 — KSZ8873MLL/FLL/RLL. TABLE 2-1:. SIGNALS (CONTINUED). Type. Pin. Note. … |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
KSZ8873MLL/FLL/RLL. TABLE 2-1:. SIGNALS (CONTINUED). Type. Pin. Note. Description. Number. Name. 2-1. Strap option:
Model Line for this Datasheet
Text Version of Document
KSZ8873MLL/FLL/RLL TABLE 2-1: SIGNALS (CONTINUED) Type Pin Pin Note Description Number Name 2-1
MLL/FLL: Switch MII transmit clock (MII mode only) Output in PHY MII mode and SNI mode SMTXC3/ Input in MAC MII and RMII mode. 26 I/O REFCLKI_3 RLL: Reference clock input Note: Pull-down by resistor is needed if internal reference clock is used in RLL by register 198 bit 3. Switch MII transmit error in MII mode SMTXER3/ 27 Ipd 0= MII link indicator from host in MII PHY mode. MII_LINK_3 1= No link on port 3 MII PHY mode and enable bypass mode. Switch MII receive data valid
Strap option:
MII mode selection 28 SMRXDV3 Ipu/O PU = PHY mode. PD = MAC mode (In MAC mode, port 3 MII has to connect a powered active external PHY for the normal operation) MLL/FLL: Switch MII receive data bit 3/ RLL: Output reference clock in RMII mode. SMRXD33/ 29 Ipu/O REFCLKO_3
Strap option:
enable auto-negotiation on port 2 (P2ANEN) PU = enable P2ANEN PD = disable P2ANEN Switch MII receive data bit 2 30 SMRXD32 Ipu/O
Strap option:
Force the speed on port 2 PU = force port 2 to 100BT if P2ANEN = 0 PD = force port 2 to 10BT if P2ANEN = 0 Switch MII/RMII receive data bit 1
Strap option:
Force duplex mode (P2DPX) PU = port 2 default to full-duplex mode if P2ANEN = 1 and auto-negotiation 31 SMRXD31 Ipu/O fails. Force port 2 in full-duplex mode if P2ANEN = 0. PD = Port 2 set to half-duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in half-duplex mode if P2ANEN = 0. 32 GND GND Digital ground Switch MII/RMII receive data bit 0
Strap option:
Force flow control on port 2 (P2FFC) 33 SMRXD30 Ipu/O PU = always enable (force) port 2 flow control feature, regardless of auto- negotiation result. PD = port 2 flow control feature is enabled by auto-negotiation result. MLL/FLL: Switch MII carrier sense RLL: No connection, internal pull-up. Note: For MLL/FLL part, when chip is configured as MAC mode, this pin 34 SCRS3/NC Ipu/O should be driven from CRS pin of PHY or from CRS pin of FPGA with a logic of (TXEN | RXDV). If only full-duplex is used, then this pin should be pull- down by 1kΩ resistor. MLL/FLL: Switch MII collision detect 35 SCOL3/NC Ipu/O RLL: No connection, internal pull-up. 2017 Microchip Technology Inc. DS00002348A-page 7 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Input Timing 7.7 SPI Output Timing 7.8 Auto-Negotiation Timing 7.9 MDC/MDIO Timing 7.10 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service
MLL/FLL: Switch MII transmit clock (MII mode only) Output in PHY MII mode and SNI mode SMTXC3/ Input in MAC MII and RMII mode. 26 I/O REFCLKI_3 RLL: Reference clock input Note: Pull-down by resistor is needed if internal reference clock is used in RLL by register 198 bit 3. Switch MII transmit error in MII mode SMTXER3/ 27 Ipd 0= MII link indicator from host in MII PHY mode. MII_LINK_3 1= No link on port 3 MII PHY mode and enable bypass mode. Switch MII receive data valid
Strap option:
MII mode selection 28 SMRXDV3 Ipu/O PU = PHY mode. PD = MAC mode (In MAC mode, port 3 MII has to connect a powered active external PHY for the normal operation) MLL/FLL: Switch MII receive data bit 3/ RLL: Output reference clock in RMII mode. SMRXD33/ 29 Ipu/O REFCLKO_3
Strap option:
enable auto-negotiation on port 2 (P2ANEN) PU = enable P2ANEN PD = disable P2ANEN Switch MII receive data bit 2 30 SMRXD32 Ipu/O
Strap option:
Force the speed on port 2 PU = force port 2 to 100BT if P2ANEN = 0 PD = force port 2 to 10BT if P2ANEN = 0 Switch MII/RMII receive data bit 1
Strap option:
Force duplex mode (P2DPX) PU = port 2 default to full-duplex mode if P2ANEN = 1 and auto-negotiation 31 SMRXD31 Ipu/O fails. Force port 2 in full-duplex mode if P2ANEN = 0. PD = Port 2 set to half-duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in half-duplex mode if P2ANEN = 0. 32 GND GND Digital ground Switch MII/RMII receive data bit 0
Strap option:
Force flow control on port 2 (P2FFC) 33 SMRXD30 Ipu/O PU = always enable (force) port 2 flow control feature, regardless of auto- negotiation result. PD = port 2 flow control feature is enabled by auto-negotiation result. MLL/FLL: Switch MII carrier sense RLL: No connection, internal pull-up. Note: For MLL/FLL part, when chip is configured as MAC mode, this pin 34 SCRS3/NC Ipu/O should be driven from CRS pin of PHY or from CRS pin of FPGA with a logic of (TXEN | RXDV). If only full-duplex is used, then this pin should be pull- down by 1kΩ resistor. MLL/FLL: Switch MII collision detect 35 SCOL3/NC Ipu/O RLL: No connection, internal pull-up. 2017 Microchip Technology Inc. DS00002348A-page 7 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Input Timing 7.7 SPI Output Timing 7.8 Auto-Negotiation Timing 7.9 MDC/MDIO Timing 7.10 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service
