Datasheet KSZ8893MQL, KSZ8893MBL (Microchip) - 5
| Manufacturer | Microchip |
| Description | Integrated 3-Port 10/100 Managed Switch with PHYs |
| Pages / Page | 116 / 5 — Micrel, Inc. KSZ8893MQL/MBL QoS Priority Support.48. Port-Based … |
| File Format / Size | PDF / 714 Kb |
| Document Language | English |
Micrel, Inc. KSZ8893MQL/MBL QoS Priority Support.48. Port-Based Priority.48. 802.1p-Based Priority.48
Model Line for this Datasheet
Text Version of Document
Micrel, Inc. KSZ8893MQL/MBL QoS Priority Support.48
Port-Based Priority.48
802.1p-Based Priority.48
DiffServ-Based Priority .49
Rate Limiting Support .49
Unicast MAC Address Filtering.49
Configuration Interface .50
2
I C Master Serial Bus Configuration .50
2
I C Slave Serial Bus Configuration .51
SPI Slave Serial Bus Configuration .51
Loopback Support.54
Far-end Loopback.54
Near-end (Remote) Loopback .55 MII Management (MIIM) Registers. 56
PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control.57
PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control.57
PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status.58
PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status.58
PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High .58
PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High .58
PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low .58
PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low .58
PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability .59
PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability .59
PHY1 Register 5 (PHYAD = 0x1, REGAD = 0x5): Auto-Negotiation Link Partner Ability .59
PHY2 Register 5 (PHYAD = 0x2, REGAD = 0x5): Auto-Negotiation Link Partner Ability .59
PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): LinkMD Control/Status.60
PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status.60
PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status .60
PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status .60 Register Map: Switch & PHY (8-bit registers) . 61
Global Registers .61
Port Registers .61
Advanced Control Registers .61
Global Registers.61
Register 0 (0x00): Chip ID0 .61
Register 1 (0x01): Chip ID1 / Start Switch .62
Register 2 (0x02): Global Control 0 .62
Register 3 (0x03): Global Control 1 .63
Register 4 (0x04): Global Control 2 .63
Register 4 (0x04): Global Control 2 (continued).64
Register 5 (0x05): Global Control 3 .64
Register 5 (0x05): Global Control 3 (continued).65
Register 6 (0x06): Global Control 4 .65
Register 6 (0x06): Global Control 4 (continued).66
Register 7 (0x07): Global Control 5 .66
Register 8 (0x08): Global Control 6 .66
Register 9 (0x09): Global Control 7 .66
Register 10 (0x0A): Global Control 8 .66
Register 11 (0x0B): Global Control 9 .67
Register 12 (0x0C): Global Control 10.67
Register 13 (0x0D): Global Control 11.68
Register 14 (0x0E): Global Control 12 .68
Register 15 (0x0F): Global Control 13 .68
Port Registers.68
Register 16 (0x10): Port 1 Control 0 .69
Register 32 (0x20): Port 2 Control 0 .69
Register 48 (0x30): Port 3 Control 0 .69
Register 17 (0x11): Port 1 Control 1 .70
Register 33 (0x21): Port 2 Control 1 .70
Register 49 (0x31): Port 3 Control 1 .70 February 2010 5 M9999-021110-1.6
Port-Based Priority.48
802.1p-Based Priority.48
DiffServ-Based Priority .49
Rate Limiting Support .49
Unicast MAC Address Filtering.49
Configuration Interface .50
2
I C Master Serial Bus Configuration .50
2
I C Slave Serial Bus Configuration .51
SPI Slave Serial Bus Configuration .51
Loopback Support.54
Far-end Loopback.54
Near-end (Remote) Loopback .55 MII Management (MIIM) Registers. 56
PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control.57
PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control.57
PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status.58
PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status.58
PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High .58
PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High .58
PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low .58
PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low .58
PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability .59
PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability .59
PHY1 Register 5 (PHYAD = 0x1, REGAD = 0x5): Auto-Negotiation Link Partner Ability .59
PHY2 Register 5 (PHYAD = 0x2, REGAD = 0x5): Auto-Negotiation Link Partner Ability .59
PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): LinkMD Control/Status.60
PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status.60
PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status .60
PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status .60 Register Map: Switch & PHY (8-bit registers) . 61
Global Registers .61
Port Registers .61
Advanced Control Registers .61
Global Registers.61
Register 0 (0x00): Chip ID0 .61
Register 1 (0x01): Chip ID1 / Start Switch .62
Register 2 (0x02): Global Control 0 .62
Register 3 (0x03): Global Control 1 .63
Register 4 (0x04): Global Control 2 .63
Register 4 (0x04): Global Control 2 (continued).64
Register 5 (0x05): Global Control 3 .64
Register 5 (0x05): Global Control 3 (continued).65
Register 6 (0x06): Global Control 4 .65
Register 6 (0x06): Global Control 4 (continued).66
Register 7 (0x07): Global Control 5 .66
Register 8 (0x08): Global Control 6 .66
Register 9 (0x09): Global Control 7 .66
Register 10 (0x0A): Global Control 8 .66
Register 11 (0x0B): Global Control 9 .67
Register 12 (0x0C): Global Control 10.67
Register 13 (0x0D): Global Control 11.68
Register 14 (0x0E): Global Control 12 .68
Register 15 (0x0F): Global Control 13 .68
Port Registers.68
Register 16 (0x10): Port 1 Control 0 .69
Register 32 (0x20): Port 2 Control 0 .69
Register 48 (0x30): Port 3 Control 0 .69
Register 17 (0x11): Port 1 Control 1 .70
Register 33 (0x21): Port 2 Control 1 .70
Register 49 (0x31): Port 3 Control 1 .70 February 2010 5 M9999-021110-1.6
