Datasheet AD8341 (Analog Devices) - 3

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Data Sheet AD8341 SPECIFICATIONS
VS = 5 V, TA = 25°C, ZO = 50 Ω, f = 1.9 GHz, single-ended, ac-coupled source drive to RFIP through 1.2 nH series inductor, RFIM ac-coupled through 1.2 nH series inductor to common, differential-to-single-ended conversion at output using 1:1 balun.
Table 1. Parameter Conditions Min Typ Max Unit
OVERALL FUNCTION Frequency Range 1.5 2.4 GHz Maximum Gain Maximum gain setpoint for all phase setpoints −4.5 dB Minimum Gain VBBI = VBBQ = 0 V differential −34.5 dB (at recommended common-mode level) Gain Control Range Relative to maximum gain 30 dB Phase Control Range Over 30 dB control range 360 Degrees Gain Flatness Over any 60 MHz bandwidth 0.5 dB Group Delay Flatness Over any 60 MHz bandwidth 50 ps RF INPUT STAGE RFIM, RFIP (Pins 21 and 22) Input Return Loss From RFIP to CMRF (with 1.2 nH series inductors) 12 dB CARTESIAN CONTROL INTERFACE (I AND Q) IBBP, IBBM, QBBP, QBBM (Pins 16, 15, 3, 4) Gain Scaling 2 1/V Modulation Bandwidth 500 mV p-p, sinusoidal baseband input single-ended 230 MHz Second Harmonic Distortion 500 mV p-p, 1 MHz, sinusoidal baseband input differential 41 dBc Third Harmonic Distortion 500 mV p-p, 1 MHz, sinusoidal baseband input differential 47 dBc Step Response For gain setpoint from 0.1 to 0.9 45 ns (VBBP = 0.5 V, VBBM = 0.55 V to 0.95 V) For gain setpoint from 0.9 to 0.1 45 ns (VBBP = 0.5 V, VBBM = 0.95 V to 0.55 V) Recommended Common-Mode Level 0.5 V RF OUTPUT STAGE RFOP, RFOM (Pins 9, 10) Output Return Loss Measured through balun 7.5 dB f = 1.9 GHz Gain Maximum gain setpoint −4.5 dB Output Noise Floor Maximum gain setpoint, no input −150.5 dBm/Hz PIN = 0 dBm, frequency offset = 20 MHz −149 dBm/Hz Output IP3 f1 = 1900 MHz, f2 = 1897.5 MHz, maximum gain setpoint 17.5 dBm Adjacent Channel Power CDMA2000, single carrier, POUT = -4 dBm, −76 dBm maximum gain, phase setpoint = 45° (See Figure 35) Output 1 dB Compression Point Maximum gain 8.5 dBm POWER SUPPLY VPS2 (Pins 5, 6, and 14), VPRF (Pins 19 and 24), RFOP, RFOM (Pins 9 and 10) Positive Supply Voltage 4.75 5 5.25 V Total Supply Current Includes load current 105 125 145 mA OUTPUT DISABLE DSOP (Pin 13) Disable Threshold (See Figure 24) Vs/2 V Attenuation DSOP = 5 V 33 dB Enable Response Time Delay following high-to-low transition until 30 ns RF output amplitude is within 10% of final value. Disable Response Time Delay following low-to-high transition until 15 ns device produces full attenuation Rev. B | Page 3 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RF QUADRATURE GENERATOR I-Q ATTENUATORS AND BASEBAND AMPLIFIERS OUTPUT AMPLIFIER NOISE AND DISTORTION GAIN AND PHASE ACCURACY RF FREQUENCY RANGE APPLICATIONS INFORMATION USING THE AD8341 RF INPUT AND MATCHING RF OUTPUT AND MATCHING DRIVING THE I-Q BASEBAND CONTROLS INTERFACING TO HIGH SPEED DACs CDMA2000 APPLICATION WCDMA APPLICATION EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE