Datasheet HMC394LP4, 394LP4E (Analog Devices) - 9

HMC394LP4 / 394LP4E
v09.0114
GaAs HBT PROGRAMMABLE 5-BIT COUNTER, DC - 2.2 GHz Synchronous Programming
4 For applications which can not tolerate a momentary undefined division ratio, which normal y occurs while changing 4 the data bits (A0-A4) at random, synchronous programming can be used. Data is loaded into the counter on every rising edge of the clock which occurs while the output (OUT) is “HIGH”. The typical minimum setup and hold times are t shown in the table below as a function of frequency. For precision applications, the rising edge of the complementary t M output may be used to latch the new data bits (A0-A4), so that all bits are settled before the next load cycle. M s s T = N/f (For Synchronous Programming) SETTLING MAX IN s - Where N is the desired division ratio, and f = Input Frequency (Hz) IN s - r r o o t Parameter 0.5 GHz 1 GHz 2 GHz t c t 200 ps 200 ps 200 ps c e SETUP e t t 700 ps 300 ps 120 ps HOLD t e e s & D
Programmable Divider Timing Requirements
s & D r
for Synchronous Programming Programmable Divider Timing Requirements
r e
for Synchronous Programming
e iD iD iv tSU iv y D OUT y D c c n tHOLD n e e u u q OUT Rising Edge to q e Clock New Data e r r F F A0-A4 CURRENT DATA NEW DATA IN Data Load Rising Edge Info F rmoatr p ion rfiurcne is , d hed ebly ivAe n r al y a og D n evd t ice o p s is bla eli c eve o ed t rd o b e e ras: H ccuratite tiatne M d reli iac bl reo . w Ho av wev e C er, n o o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rporation, 20 Alpha Road, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd hone e r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o t niltie n .c e ao t m
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