Datasheet LT1952, LT1952-1 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Single Switch Synchronous Forward Controller |
| Pages / Page | 28 / 9 — PIN FUNCTIONS. COMP (Pin 1):. GND (Pin 8):. BLANK (Pin 9):. ISENSE (Pin … |
| File Format / Size | PDF / 371 Kb |
| Document Language | English |
PIN FUNCTIONS. COMP (Pin 1):. GND (Pin 8):. BLANK (Pin 9):. ISENSE (Pin 10):. OC (Pin 11):. FB (Pin 2):. DELAY (Pin 12):. ROSC (Pin 3):
Model Line for this Datasheet
Text Version of Document
LT1952/LT1952-1
PIN FUNCTIONS COMP (Pin 1):
Output Pin of the Error Amplifier. The error
GND (Pin 8):
Analog Ground. amplifier is an op amp, allowing various compensation
BLANK (Pin 9):
A resistor to ground adjusts the extended networks to be connected between the COMP pin and blanking period of the overcurrent and current sense FB pin for optimum transient response. The voltage on amplifier outputs during FET turn on—to prevent false this pin corresponds to the peak current of the external current limit trip. Increasing the resistor value increases FET. Full operating voltage range is between 0.8V and the blanking period. 2.5V corresponding to 0mV to 220mV at the ISENSE pin. For applications using the 100mV OC pin for overcurrent
ISENSE (Pin 10):
The Current Sense Input for the Control detection, typical operating range for the COMP pin is Loop. Connect this pin to the sense resistor in the source 0.8V to 1.6V. For isolated applications where COMP is of the external power MOSFET. A resistor in series with controlled by an opto-coupler, the COMP pin output drive the ISENSE pin programs slope compensation. can be disabled with FB = VREF, reducing the COMP pin
OC (Pin 11):
An accurate 107mV threshold, independent current to (COMP – 0.7)/40k. of duty cycle, for overcurrent detection and trigger of
FB (Pin 2):
Monitors the output voltage via an external soft-start. Connect this pin directly to the sense resistor resistor divider and is compared with an internal 1.23V in the source of the external power MOSFET. reference by the error amplifier. FB connected to VREF
DELAY (Pin 12):
A resistor to ground adjusts the delay disables error amplifier output. period between SOUT rising edge and OUT rising edge.
ROSC (Pin 3):
A resistor to ground programs the operating Used to maximize efficiency in forward converter applica- frequency of the IC between 100kHz and 500kHz. Nominal tions by adjusting the control timing of secondary side voltage on the ROSC pin is 1.0V. synchronous rectifier MOSFETs. Increasing the resistor value increases the delay period.
SYNC (Pin 4):
Used to Synchronize the Internal Oscillator to an External Signal. It is directly logic compatible and
PGND (Pin 13):
Power Ground. can be driven with any signal between 10% and 90% duty
OUT (Pin 14):
Drives the Gate of an N-channel MOSFET cycle. If unused, the pin can be left open or connected to between 0V and V ground. IN with a maximum limit of 13V on OUT pin set by an internal clamp. Active pull-off exists in
SS_MAXDC (Pin 5):
External resistor divider from VREF shutdown (see electrical specification). sets maximum duty cycle clamp (SS_MAXDC = 1.84V,
V
SD_V
IN (Pin 15):
Input Supply for the Part. It must be closely SEC = 1.32V gives 72% duty cycle). Capacitor on decoupled to ground. An internal undervoltage lockout SS_MAXDC pin in combination with external resistor threshold exists for V divider sets soft-start timing. IN at approximately 14.25V on and 8.75V off for the LT1952. The LT1952-1 has lower
VREF (Pin 6):
The output of an internal 2.5V reference which undervoltage lockout thresholds set at 7.75V on and supplies control circuitry in the IC. Capable of sourcing up 6.5V off. to 2.5mA drive for external use. Bypass to ground with a
SOUT (Pin 16):
Switched Output in Phase with OUT Pin. 0.1µF ceramic capacitor. Provides sync signal for control of secondary side FETs
SD_VSEC (Pin 7):
The SD_VSEC pin, when pulled below in forward converter applications requiring highly efficient its accurate 1.32V threshold, is used to turn off the IC synchronous rectification. SOUT is actively clamped to and reduce current drain from VIN. The SD_VSEC pin is 12V. Active pull-off exists in shutdown (see electrical connected to system input voltage through a resistor specification). divider to define undervoltage lockout (UVLO) and to provide a Volt-Second clamp on the OUT pin. A 10µA pin current hysteresis allows external programming of UVLO hysteresis. 19521fe 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Timing Diagram Block Diagram Operation Applications Information Typical Applications Revision History Package Description Related Parts
PIN FUNCTIONS COMP (Pin 1):
Output Pin of the Error Amplifier. The error
GND (Pin 8):
Analog Ground. amplifier is an op amp, allowing various compensation
BLANK (Pin 9):
A resistor to ground adjusts the extended networks to be connected between the COMP pin and blanking period of the overcurrent and current sense FB pin for optimum transient response. The voltage on amplifier outputs during FET turn on—to prevent false this pin corresponds to the peak current of the external current limit trip. Increasing the resistor value increases FET. Full operating voltage range is between 0.8V and the blanking period. 2.5V corresponding to 0mV to 220mV at the ISENSE pin. For applications using the 100mV OC pin for overcurrent
ISENSE (Pin 10):
The Current Sense Input for the Control detection, typical operating range for the COMP pin is Loop. Connect this pin to the sense resistor in the source 0.8V to 1.6V. For isolated applications where COMP is of the external power MOSFET. A resistor in series with controlled by an opto-coupler, the COMP pin output drive the ISENSE pin programs slope compensation. can be disabled with FB = VREF, reducing the COMP pin
OC (Pin 11):
An accurate 107mV threshold, independent current to (COMP – 0.7)/40k. of duty cycle, for overcurrent detection and trigger of
FB (Pin 2):
Monitors the output voltage via an external soft-start. Connect this pin directly to the sense resistor resistor divider and is compared with an internal 1.23V in the source of the external power MOSFET. reference by the error amplifier. FB connected to VREF
DELAY (Pin 12):
A resistor to ground adjusts the delay disables error amplifier output. period between SOUT rising edge and OUT rising edge.
ROSC (Pin 3):
A resistor to ground programs the operating Used to maximize efficiency in forward converter applica- frequency of the IC between 100kHz and 500kHz. Nominal tions by adjusting the control timing of secondary side voltage on the ROSC pin is 1.0V. synchronous rectifier MOSFETs. Increasing the resistor value increases the delay period.
SYNC (Pin 4):
Used to Synchronize the Internal Oscillator to an External Signal. It is directly logic compatible and
PGND (Pin 13):
Power Ground. can be driven with any signal between 10% and 90% duty
OUT (Pin 14):
Drives the Gate of an N-channel MOSFET cycle. If unused, the pin can be left open or connected to between 0V and V ground. IN with a maximum limit of 13V on OUT pin set by an internal clamp. Active pull-off exists in
SS_MAXDC (Pin 5):
External resistor divider from VREF shutdown (see electrical specification). sets maximum duty cycle clamp (SS_MAXDC = 1.84V,
V
SD_V
IN (Pin 15):
Input Supply for the Part. It must be closely SEC = 1.32V gives 72% duty cycle). Capacitor on decoupled to ground. An internal undervoltage lockout SS_MAXDC pin in combination with external resistor threshold exists for V divider sets soft-start timing. IN at approximately 14.25V on and 8.75V off for the LT1952. The LT1952-1 has lower
VREF (Pin 6):
The output of an internal 2.5V reference which undervoltage lockout thresholds set at 7.75V on and supplies control circuitry in the IC. Capable of sourcing up 6.5V off. to 2.5mA drive for external use. Bypass to ground with a
SOUT (Pin 16):
Switched Output in Phase with OUT Pin. 0.1µF ceramic capacitor. Provides sync signal for control of secondary side FETs
SD_VSEC (Pin 7):
The SD_VSEC pin, when pulled below in forward converter applications requiring highly efficient its accurate 1.32V threshold, is used to turn off the IC synchronous rectification. SOUT is actively clamped to and reduce current drain from VIN. The SD_VSEC pin is 12V. Active pull-off exists in shutdown (see electrical connected to system input voltage through a resistor specification). divider to define undervoltage lockout (UVLO) and to provide a Volt-Second clamp on the OUT pin. A 10µA pin current hysteresis allows external programming of UVLO hysteresis. 19521fe 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Timing Diagram Block Diagram Operation Applications Information Typical Applications Revision History Package Description Related Parts
