Datasheet LT1952, LT1952-1 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Single Switch Synchronous Forward Controller |
| Pages / Page | 28 / 10 — TIMING DIAGRAM. Figure 1. Timing Diagram. BLOCK DIAGRAM. Figure 2. Block … |
| File Format / Size | PDF / 371 Kb |
| Document Language | English |
TIMING DIAGRAM. Figure 1. Timing Diagram. BLOCK DIAGRAM. Figure 2. Block Diagram
Model Line for this Datasheet
Text Version of Document
LT1952/LT1952-1
TIMING DIAGRAM
tDELAY: PROGRAMMABLE SYNCHRONOUS DELAY SOUT OUT SS_MAXDC FAULTS TRIGGERING SOFT-START VIN < 8.75V OR SD_V 0.8V (ACTIVE THRESHOLD) SEC < 1.32V (UVLO) OR 0.45V (RESET THRESHOLD) OC > 107mV (OVERCURRENT) 0.2V SOFT-START LATCH RESET: SOFT-START VIN > 14.25V (> 8.75V IF LATCH SET BY OC) LATCH SET AND SD_VSEC > 1.32V AND OC < 107mV AND SS_MAXDC < 0.45V 1952 F01
Figure 1. Timing Diagram BLOCK DIAGRAM
VIN VREF SS_MAXDC 15 6 5 START-UP LT1952 VINON INPUT CURRENT (ISTART) VREF I VINOFF START = 460µA 0.45V + >90% V SOFT-START CONTROL IN ON = 14.25V VIN OFF = 8.75V – + 2.5V – LT1952-1 I SOURCE R START = 400µA V 2.5mA IN ON = 7.75V Q VIN OFF = 6.5V – S + ±50mA 1.23V ADAPTIVE MAXIMUM 16 SOUT – DUTY CYCLE CLAMP 12V IHYST 10µA SD_VSEC = 1.32V 0µA SD_V + SEC > 1.32V – + (TYPICAL 200kHz) SD_V ON SEC 7 OSC 1.32V S Q DRIVER 14 OUT DELAY ±1A ROSC 3 (100 TO 500)kHz (LINEAR) R SLOPE COMP RAMP 13 PGND 8µA 0% DC 35µA 80% DC SYNC 4 13V BLANK (VOLTAGE) + ERROR AMPLIFIER 1.23V SENSE OVER – + CURRENT + CURRENT – – 11 OC 0mV TO 220mV 107mV 10 ISENSE 2 1 8 12 9 1952 BD FB COMP GND DELAY BLANK
Figure 2. Block Diagram
19521fe 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Timing Diagram Block Diagram Operation Applications Information Typical Applications Revision History Package Description Related Parts
TIMING DIAGRAM
tDELAY: PROGRAMMABLE SYNCHRONOUS DELAY SOUT OUT SS_MAXDC FAULTS TRIGGERING SOFT-START VIN < 8.75V OR SD_V 0.8V (ACTIVE THRESHOLD) SEC < 1.32V (UVLO) OR 0.45V (RESET THRESHOLD) OC > 107mV (OVERCURRENT) 0.2V SOFT-START LATCH RESET: SOFT-START VIN > 14.25V (> 8.75V IF LATCH SET BY OC) LATCH SET AND SD_VSEC > 1.32V AND OC < 107mV AND SS_MAXDC < 0.45V 1952 F01
Figure 1. Timing Diagram BLOCK DIAGRAM
VIN VREF SS_MAXDC 15 6 5 START-UP LT1952 VINON INPUT CURRENT (ISTART) VREF I VINOFF START = 460µA 0.45V + >90% V SOFT-START CONTROL IN ON = 14.25V VIN OFF = 8.75V – + 2.5V – LT1952-1 I SOURCE R START = 400µA V 2.5mA IN ON = 7.75V Q VIN OFF = 6.5V – S + ±50mA 1.23V ADAPTIVE MAXIMUM 16 SOUT – DUTY CYCLE CLAMP 12V IHYST 10µA SD_VSEC = 1.32V 0µA SD_V + SEC > 1.32V – + (TYPICAL 200kHz) SD_V ON SEC 7 OSC 1.32V S Q DRIVER 14 OUT DELAY ±1A ROSC 3 (100 TO 500)kHz (LINEAR) R SLOPE COMP RAMP 13 PGND 8µA 0% DC 35µA 80% DC SYNC 4 13V BLANK (VOLTAGE) + ERROR AMPLIFIER 1.23V SENSE OVER – + CURRENT + CURRENT – – 11 OC 0mV TO 220mV 107mV 10 ISENSE 2 1 8 12 9 1952 BD FB COMP GND DELAY BLANK
Figure 2. Block Diagram
19521fe 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Timing Diagram Block Diagram Operation Applications Information Typical Applications Revision History Package Description Related Parts
