Datasheet ADM1041A (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Secondary-Side Controller with Current Share and Housekeeping |
| Pages / Page | 56 / 4 — ADM1041A. SHARE BUS. REMOTE. –VE SENSE. 1N4148. /R2. 12V. DRAI. 1 + R2). … |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
ADM1041A. SHARE BUS. REMOTE. –VE SENSE. 1N4148. /R2. 12V. DRAI. 1 + R2). = ( N. GATE. /SHRS. GAI. SCMP. SHRO. SHRS+. SOURCE. ROL. 50k. CONT. POLARI
Model Line for this Datasheet
Text Version of Document
ADM1041A R1 R2 SHARE BUS REMOTE –VE SENSE T OU 1N4148 V N /R2 12V DRAI 1 + R2) – R = ( N GATE DD /SHRS V GAI G S– F SCMP SHRO SHRS+ V SOURCE 19 22 24 23 20
Ω Ω Ω
ROL
μ
A TY 50k 60 50k 50k L CONT VE R A POLARI T
Ω
IE E I SHARE CLAMP IF R DRI L 50k IE P + 10V ORF IF M SENSE T ERROR L A P I SHARE FFERENTI OU M DI A I SHARE 50mV V = V FET OK Or 50mV REVERSEOK HARE TO VOLTAGE ERROR AMP S REFV NT PENOK LOADVOK REVERSE VOLTAGE DETECTOR CURRE DF SHAREOK 6 IT IM L 9R LS /V 2 ERROR AMP FS R CURRENT- –/ S C DD 3 V CURRENT REF + S V C REFV , ) 0 = T LEVEL T SHARE MI SHARE U OFFSET (V LI IO CURRENT SET CURRENT- SE AC_OK SET SHARE SEN PULSEOK CURRENT C A / S T IR IC SQ R SQ R N Q Q SET GAI CLK 1 Sec CLK 1 mSec R R REG 17h b7 S 0
Ω
525V 1 0. = 40k E 5V M IN 1. A NS TRI HYSTERESI G E S
Ω
SENSE 3k NT 5. SELECT AC
Ω
3k CURRE 5. 9 8 4 1 10 2 T P IC CMC PULSE SENSE SENSE AC AC URATON G SENSE CURRENT- CURRENT TRANSFORMER CONFI TRANSFORMER
05405-003 Figure 3. ADM1041A Diagram, Part 1 Rev. 0 | Page 4 of 56 Document Outline FEATURES SECONDARY-SIDE FEATURES INTERFACE AND INTERNAL FEATURES APPLICATIONS GENERAL DESCRIPTION SAMPLE APPLICATION CIRCUIT DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION POWER MANAGEMENT GAIN TRIMMING AND CONFIGURATION DIFFERENTIAL REMOTE SENSE AMPLIFIER SET LOAD VOLTAGE LOAD OVERVOLTAGE (OV) LOCAL VOLTAGE SENSE LOCAL OVERVOLTAGE PROTECTION (OVP) LOCAL UNDERVOLTAGE PROTECTION (UVP) FALSE UV CLAMP VOLTAGE ERROR AMPLIFIER MAIN VOLTAGE REFERENCE CURRENT-SENSE AMPLIFIER CURRENT SENSING CURRENT-TRANSFORMER INPUT CURRENT-SENSE CALIBRATION CURRENT-LIMIT ERROR AMPLIFIER OVERCURRENT PROTECTION CURRENT SHARE CURRENT-SHARE OFFSET ISHARE DRIVE AMPLIFIER DIFFERENTIAL SENSE AMPLIFIER ISHARE ERROR AMPLIFIER ISHARE CLAMP SHARE_OK DETECTOR PULSE/ACSENSE2 PULSE ACSENSE OrFET GATE DRIVE OSCILLATOR AND TIMING GENERATORS LOGIC I/O AND MONITOR PINS CBD/ALERT MON1 MON2 PEN PSON MON3 DC_OK (POWER-OK, POWER Good, Etc.) MON4 AC_OK MON5 SMBus SERIAL PORT MICROPROCESSOR SUPPORT Interfacing Configuring for a Microprocessor BROADCASTING SMBus SERIAL INTERFACE GENERAL SMBus TIMING SMBus PROTOCOLS FOR RAM AND EEPROM SMBus Erase EEPROM Page Operations SMBus Write Operations Send Byte Write Byte/Word Block Write SMBus READ OPERATIONS Receive Byte Block Read Notes on SMBus Read Operations SMBus ALERT RESPONSE ADDRESS (ARA) SUPPORT FOR SMBus 1.1 LAYOUT CONSIDERATIONS POWER-UP AUTO-CONFIGURATION EXTENDED SMBus ADDRESSING SDA/PSONLINK SCL/AC_OKLink BACKDOOR ACCESS REGISTER LISTING DETAILED REGISTER DESCRIPTIONS MANUFACTURING DATA MICROPROCESSOR SUPPORT TEST NAME TABLE OUTLINE DIMENSIONS ORDERING GUIDE
Ω Ω Ω
ROL
μ
A TY 50k 60 50k 50k L CONT VE R A POLARI T
Ω
IE E I SHARE CLAMP IF R DRI L 50k IE P + 10V ORF IF M SENSE T ERROR L A P I SHARE FFERENTI OU M DI A I SHARE 50mV V = V FET OK Or 50mV REVERSEOK HARE TO VOLTAGE ERROR AMP S REFV NT PENOK LOADVOK REVERSE VOLTAGE DETECTOR CURRE DF SHAREOK 6 IT IM L 9R LS /V 2 ERROR AMP FS R CURRENT- –/ S C DD 3 V CURRENT REF + S V C REFV , ) 0 = T LEVEL T SHARE MI SHARE U OFFSET (V LI IO CURRENT SET CURRENT- SE AC_OK SET SHARE SEN PULSEOK CURRENT C A / S T IR IC SQ R SQ R N Q Q SET GAI CLK 1 Sec CLK 1 mSec R R REG 17h b7 S 0
Ω
525V 1 0. = 40k E 5V M IN 1. A NS TRI HYSTERESI G E S
Ω
SENSE 3k NT 5. SELECT AC
Ω
3k CURRE 5. 9 8 4 1 10 2 T P IC CMC PULSE SENSE SENSE AC AC URATON G SENSE CURRENT- CURRENT TRANSFORMER CONFI TRANSFORMER
05405-003 Figure 3. ADM1041A Diagram, Part 1 Rev. 0 | Page 4 of 56 Document Outline FEATURES SECONDARY-SIDE FEATURES INTERFACE AND INTERNAL FEATURES APPLICATIONS GENERAL DESCRIPTION SAMPLE APPLICATION CIRCUIT DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION POWER MANAGEMENT GAIN TRIMMING AND CONFIGURATION DIFFERENTIAL REMOTE SENSE AMPLIFIER SET LOAD VOLTAGE LOAD OVERVOLTAGE (OV) LOCAL VOLTAGE SENSE LOCAL OVERVOLTAGE PROTECTION (OVP) LOCAL UNDERVOLTAGE PROTECTION (UVP) FALSE UV CLAMP VOLTAGE ERROR AMPLIFIER MAIN VOLTAGE REFERENCE CURRENT-SENSE AMPLIFIER CURRENT SENSING CURRENT-TRANSFORMER INPUT CURRENT-SENSE CALIBRATION CURRENT-LIMIT ERROR AMPLIFIER OVERCURRENT PROTECTION CURRENT SHARE CURRENT-SHARE OFFSET ISHARE DRIVE AMPLIFIER DIFFERENTIAL SENSE AMPLIFIER ISHARE ERROR AMPLIFIER ISHARE CLAMP SHARE_OK DETECTOR PULSE/ACSENSE2 PULSE ACSENSE OrFET GATE DRIVE OSCILLATOR AND TIMING GENERATORS LOGIC I/O AND MONITOR PINS CBD/ALERT MON1 MON2 PEN PSON MON3 DC_OK (POWER-OK, POWER Good, Etc.) MON4 AC_OK MON5 SMBus SERIAL PORT MICROPROCESSOR SUPPORT Interfacing Configuring for a Microprocessor BROADCASTING SMBus SERIAL INTERFACE GENERAL SMBus TIMING SMBus PROTOCOLS FOR RAM AND EEPROM SMBus Erase EEPROM Page Operations SMBus Write Operations Send Byte Write Byte/Word Block Write SMBus READ OPERATIONS Receive Byte Block Read Notes on SMBus Read Operations SMBus ALERT RESPONSE ADDRESS (ARA) SUPPORT FOR SMBus 1.1 LAYOUT CONSIDERATIONS POWER-UP AUTO-CONFIGURATION EXTENDED SMBus ADDRESSING SDA/PSONLINK SCL/AC_OKLink BACKDOOR ACCESS REGISTER LISTING DETAILED REGISTER DESCRIPTIONS MANUFACTURING DATA MICROPROCESSOR SUPPORT TEST NAME TABLE OUTLINE DIMENSIONS ORDERING GUIDE
