Datasheet ADM1041A (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | Secondary-Side Controller with Current Share and Housekeeping |
| Pages / Page | 56 / 3 — ADM1041A. GENERAL DESCRIPTION. SAMPLE APPLICATION CIRCUIT DESCRIPTION. … |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
ADM1041A. GENERAL DESCRIPTION. SAMPLE APPLICATION CIRCUIT DESCRIPTION. RSENSE. LOAD. PWM +. PRIMARY. DRIVER. AC PULSE. DIFF CURRENT. OrFET
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ADM1041A GENERAL DESCRIPTION
The ADM1041A is a secondary-side and management IC spec- Another key feature of the ADM1041A is its control of an ifically designed to minimize external component counts and to OrFET. The OrFET causes lower power dissipation across the eliminate the need for manual calibration or adjustment on the OR'ing diode. The main function of the OrFET is to disconnect secondary-side controller. The principle application of this IC is the power supply from the load in the event of a fault occurring to provide voltage control, current share, and housekeeping during steady state operation, for example, if a filter capacitor or functions for single output in N+1 server power supplies. rectifier fails and causes a short. This eliminates the risk of bringing down the load voltage that is supplied by the redun- The ADM1041A is manufactured with a 5 V CMOS process dant configuration of other power supplies. In the case of a and combines digital and analog circuitry. An internal short, a reverse voltage is generated across the OrFET. This EEPROM provides added flexibility for trimming timing and reverse voltage is detected by the ADM1041A and the OrFET is voltage and selecting various functions. Programming is done shut down via the FG pin. This intervention prevents any via an SMBus serial port that also allows communication interruption on the power supply bus. The ADM1041A can capability with a microprocessor or microcontroller. then be interrogated via the serial interface to determine why The usual configuration using this IC is on a one-per-output the power supply has shut down. voltage rail. Output from the IC can be wire-OR’ed together or This application circuit also demonstrates how temperature can bused in parallel and read by a microprocessor. A key feature on be monitored within a power supply. A thermistor is connected this IC is support for an OrFET circuit when higher efficiency between the VDD and MON2 pins. The thermistor’s voltage or power density is required. varies with temperature. The MON2 input can be programmed
SAMPLE APPLICATION CIRCUIT DESCRIPTION
to trip a flag at a voltage corresponding to an overheating power supply. The resulting action may be to turn on an additional Figure 1 shows a sample application circuit using the cooling fan to help regulate the temperature within the power ADM1041A. The primary side is not detailed and the focus is supply. on the secondary side of the power supply.
RSENSE LOAD PWM +
The ADM1041A controls the output voltage from the power
PRIMARY DRIVER
supply to the designed programmed value. This programmed value is determined during power supply design and is digitally adjusted via the serial interface. Digital adjustment of the
AC PULSE DIFF CURRENT OrFET OPTO- SENSE SENSE CONTROL
current sense and current limit is also calibrated via the serial
COUPLER
interface, as are all of the internal timing specifications.
CURRENT SHARE ERROR SHARE BUS AMP SOFT
The control loop consists of a number of elements, notably the
START DIFF LOAD AND LOCAL
inputs to the loop and the output of the loop. The ADM1041A
VOLTAGE SENSE (
μ
C OR STANDALONE VOLT, TEMP MONITOR
takes the loop inputs and determines what, if any, adjustments
OPERATION) AND FAULT DETECTION EEPROM AND SMBus
μ
C
002
RAM AND TRIM
are needed to maintain a stable output. To maintain a stable
ADM1041A
05405- loop, the ADM1041A uses three main inputs: Figure 2. Application Block Diagram • Remote voltage sense Differences Between the ADM1041A and ADM1041 • Load current sense • For all new designs, it is recommended to use the ADM1041A. Current sharing information The parts differ as follows: In this example, a resistor divider senses the output current as a voltage drop across a sense resistor (RS) and feeds a portion • The ADM1041 allows the internal VREF voltage reference to into the ADM1041A. Remote local voltage sense is monitored be accessed at Pin 18. This is not accessible using the via VS+ and VS− pins. Finally, current sharing information is fed ADM1041A. back via the share bus. These three elements are summed • The ADM1041A has longer VDDOK debounce and VDDOV together to generate a control signal (VCMP), which closes the debounce than the ADM1041. loop via an optocoupler to the primary side PWM controller. • The GND_OK Disable bit (Register 11h) does not disable when using the ADM1041. It does disable when using the ADM1041A. Rev. 0 | Page 3 of 56 Document Outline FEATURES SECONDARY-SIDE FEATURES INTERFACE AND INTERNAL FEATURES APPLICATIONS GENERAL DESCRIPTION SAMPLE APPLICATION CIRCUIT DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION POWER MANAGEMENT GAIN TRIMMING AND CONFIGURATION DIFFERENTIAL REMOTE SENSE AMPLIFIER SET LOAD VOLTAGE LOAD OVERVOLTAGE (OV) LOCAL VOLTAGE SENSE LOCAL OVERVOLTAGE PROTECTION (OVP) LOCAL UNDERVOLTAGE PROTECTION (UVP) FALSE UV CLAMP VOLTAGE ERROR AMPLIFIER MAIN VOLTAGE REFERENCE CURRENT-SENSE AMPLIFIER CURRENT SENSING CURRENT-TRANSFORMER INPUT CURRENT-SENSE CALIBRATION CURRENT-LIMIT ERROR AMPLIFIER OVERCURRENT PROTECTION CURRENT SHARE CURRENT-SHARE OFFSET ISHARE DRIVE AMPLIFIER DIFFERENTIAL SENSE AMPLIFIER ISHARE ERROR AMPLIFIER ISHARE CLAMP SHARE_OK DETECTOR PULSE/ACSENSE2 PULSE ACSENSE OrFET GATE DRIVE OSCILLATOR AND TIMING GENERATORS LOGIC I/O AND MONITOR PINS CBD/ALERT MON1 MON2 PEN PSON MON3 DC_OK (POWER-OK, POWER Good, Etc.) MON4 AC_OK MON5 SMBus SERIAL PORT MICROPROCESSOR SUPPORT Interfacing Configuring for a Microprocessor BROADCASTING SMBus SERIAL INTERFACE GENERAL SMBus TIMING SMBus PROTOCOLS FOR RAM AND EEPROM SMBus Erase EEPROM Page Operations SMBus Write Operations Send Byte Write Byte/Word Block Write SMBus READ OPERATIONS Receive Byte Block Read Notes on SMBus Read Operations SMBus ALERT RESPONSE ADDRESS (ARA) SUPPORT FOR SMBus 1.1 LAYOUT CONSIDERATIONS POWER-UP AUTO-CONFIGURATION EXTENDED SMBus ADDRESSING SDA/PSONLINK SCL/AC_OKLink BACKDOOR ACCESS REGISTER LISTING DETAILED REGISTER DESCRIPTIONS MANUFACTURING DATA MICROPROCESSOR SUPPORT TEST NAME TABLE OUTLINE DIMENSIONS ORDERING GUIDE
ADM1041A GENERAL DESCRIPTION
The ADM1041A is a secondary-side and management IC spec- Another key feature of the ADM1041A is its control of an ifically designed to minimize external component counts and to OrFET. The OrFET causes lower power dissipation across the eliminate the need for manual calibration or adjustment on the OR'ing diode. The main function of the OrFET is to disconnect secondary-side controller. The principle application of this IC is the power supply from the load in the event of a fault occurring to provide voltage control, current share, and housekeeping during steady state operation, for example, if a filter capacitor or functions for single output in N+1 server power supplies. rectifier fails and causes a short. This eliminates the risk of bringing down the load voltage that is supplied by the redun- The ADM1041A is manufactured with a 5 V CMOS process dant configuration of other power supplies. In the case of a and combines digital and analog circuitry. An internal short, a reverse voltage is generated across the OrFET. This EEPROM provides added flexibility for trimming timing and reverse voltage is detected by the ADM1041A and the OrFET is voltage and selecting various functions. Programming is done shut down via the FG pin. This intervention prevents any via an SMBus serial port that also allows communication interruption on the power supply bus. The ADM1041A can capability with a microprocessor or microcontroller. then be interrogated via the serial interface to determine why The usual configuration using this IC is on a one-per-output the power supply has shut down. voltage rail. Output from the IC can be wire-OR’ed together or This application circuit also demonstrates how temperature can bused in parallel and read by a microprocessor. A key feature on be monitored within a power supply. A thermistor is connected this IC is support for an OrFET circuit when higher efficiency between the VDD and MON2 pins. The thermistor’s voltage or power density is required. varies with temperature. The MON2 input can be programmed
SAMPLE APPLICATION CIRCUIT DESCRIPTION
to trip a flag at a voltage corresponding to an overheating power supply. The resulting action may be to turn on an additional Figure 1 shows a sample application circuit using the cooling fan to help regulate the temperature within the power ADM1041A. The primary side is not detailed and the focus is supply. on the secondary side of the power supply.
RSENSE LOAD PWM +
The ADM1041A controls the output voltage from the power
PRIMARY DRIVER
supply to the designed programmed value. This programmed value is determined during power supply design and is digitally adjusted via the serial interface. Digital adjustment of the
AC PULSE DIFF CURRENT OrFET OPTO- SENSE SENSE CONTROL
current sense and current limit is also calibrated via the serial
COUPLER
interface, as are all of the internal timing specifications.
CURRENT SHARE ERROR SHARE BUS AMP SOFT
The control loop consists of a number of elements, notably the
START DIFF LOAD AND LOCAL
inputs to the loop and the output of the loop. The ADM1041A
VOLTAGE SENSE (
μ
C OR STANDALONE VOLT, TEMP MONITOR
takes the loop inputs and determines what, if any, adjustments
OPERATION) AND FAULT DETECTION EEPROM AND SMBus
μ
C
002
RAM AND TRIM
are needed to maintain a stable output. To maintain a stable
ADM1041A
05405- loop, the ADM1041A uses three main inputs: Figure 2. Application Block Diagram • Remote voltage sense Differences Between the ADM1041A and ADM1041 • Load current sense • For all new designs, it is recommended to use the ADM1041A. Current sharing information The parts differ as follows: In this example, a resistor divider senses the output current as a voltage drop across a sense resistor (RS) and feeds a portion • The ADM1041 allows the internal VREF voltage reference to into the ADM1041A. Remote local voltage sense is monitored be accessed at Pin 18. This is not accessible using the via VS+ and VS− pins. Finally, current sharing information is fed ADM1041A. back via the share bus. These three elements are summed • The ADM1041A has longer VDDOK debounce and VDDOV together to generate a control signal (VCMP), which closes the debounce than the ADM1041. loop via an optocoupler to the primary side PWM controller. • The GND_OK Disable bit (Register 11h) does not disable when using the ADM1041. It does disable when using the ADM1041A. Rev. 0 | Page 3 of 56 Document Outline FEATURES SECONDARY-SIDE FEATURES INTERFACE AND INTERNAL FEATURES APPLICATIONS GENERAL DESCRIPTION SAMPLE APPLICATION CIRCUIT DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION POWER MANAGEMENT GAIN TRIMMING AND CONFIGURATION DIFFERENTIAL REMOTE SENSE AMPLIFIER SET LOAD VOLTAGE LOAD OVERVOLTAGE (OV) LOCAL VOLTAGE SENSE LOCAL OVERVOLTAGE PROTECTION (OVP) LOCAL UNDERVOLTAGE PROTECTION (UVP) FALSE UV CLAMP VOLTAGE ERROR AMPLIFIER MAIN VOLTAGE REFERENCE CURRENT-SENSE AMPLIFIER CURRENT SENSING CURRENT-TRANSFORMER INPUT CURRENT-SENSE CALIBRATION CURRENT-LIMIT ERROR AMPLIFIER OVERCURRENT PROTECTION CURRENT SHARE CURRENT-SHARE OFFSET ISHARE DRIVE AMPLIFIER DIFFERENTIAL SENSE AMPLIFIER ISHARE ERROR AMPLIFIER ISHARE CLAMP SHARE_OK DETECTOR PULSE/ACSENSE2 PULSE ACSENSE OrFET GATE DRIVE OSCILLATOR AND TIMING GENERATORS LOGIC I/O AND MONITOR PINS CBD/ALERT MON1 MON2 PEN PSON MON3 DC_OK (POWER-OK, POWER Good, Etc.) MON4 AC_OK MON5 SMBus SERIAL PORT MICROPROCESSOR SUPPORT Interfacing Configuring for a Microprocessor BROADCASTING SMBus SERIAL INTERFACE GENERAL SMBus TIMING SMBus PROTOCOLS FOR RAM AND EEPROM SMBus Erase EEPROM Page Operations SMBus Write Operations Send Byte Write Byte/Word Block Write SMBus READ OPERATIONS Receive Byte Block Read Notes on SMBus Read Operations SMBus ALERT RESPONSE ADDRESS (ARA) SUPPORT FOR SMBus 1.1 LAYOUT CONSIDERATIONS POWER-UP AUTO-CONFIGURATION EXTENDED SMBus ADDRESSING SDA/PSONLINK SCL/AC_OKLink BACKDOOR ACCESS REGISTER LISTING DETAILED REGISTER DESCRIPTIONS MANUFACTURING DATA MICROPROCESSOR SUPPORT TEST NAME TABLE OUTLINE DIMENSIONS ORDERING GUIDE
