Datasheet LT3710 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Secondary Side Synchronous Post Regulator |
| Pages / Page | 12 / 5 — PI FU CTIO S. BOOST (Pin 1):. BGS (Pin 9):. TGATE (Pin 2):. VAOUT (Pin … |
| File Format / Size | PDF / 228 Kb |
| Document Language | English |
PI FU CTIO S. BOOST (Pin 1):. BGS (Pin 9):. TGATE (Pin 2):. VAOUT (Pin 10):. SW (Pin 3):. CL+ (Pin 11):. CSET (Pin 4):. CL– (Pin 12):
Model Line for this Datasheet
Text Version of Document
LT3710
U U U PI FU CTIO S BOOST (Pin 1):
Topside (Boosted) Driver Supply. This pin
BGS (Pin 9):
Bottom Gate Switching Control. CA2 moni- is used to bootstrap and supply the topside power switch tors the inductor current and prohibits BGATE from turn- gate drive circuitry. In normal operation VBOOST is powered ing on when the inductor current is low (below 8mV across from the internally generated 8V GBIAS, VBOOST = VSW + the current sense resistor RS1) to allow discontinous 8.2V when TGATE is on. mode operation. Grounding this pin disables comparator CA2.
TGATE (Pin 2):
Topside (Boosted) N-Channel MOSFET Driver. When TGATE is on, the voltage is equal to VSW + 6V.
VAOUT (Pin 10):
Voltage Amplifier Output.
SW (Pin 3):
Switch Node Connection to Inductor.
CL+ (Pin 11):
Current Limit Amplifier Positive Input. The threshold is set at 70mV.
CSET (Pin 4):
Oscillator Timing Pin. The capacitor on this pin sets the PWM switching frequency.
CL– (Pin 12):
Current Limit Amplifier Negative Input. When used, CL– is connected to the output capacitor side
SYNC (Pin 5):
Synchronization Input. This pin should be of the current + sense resistor and CL+ is connected to the connected to the secondary side output of the power inductor side of the current sense resistor. transformer with a series resistor. A filtering capacitor of 10pF is recommended.
VCC (Pin 13):
Supply of the IC. For proper bypassing, a low ESR capacitor is required.
ILCOMP (Pin 6):
Current Limit Amplifier Compensation Node. At current limit, CA1 pulls down on this pin to
PGND (Pin 14):
Ground of the Bottom Side N-Channel regulate the output current. MOSFET Driver.
SS (Pin 7):
Soft-Start. A capacitor on this pin sets the
BGATE (Pin 15):
Bottom Side N-Channel MOSFET Driver. output ramp up rate. The typical time for SS to reach the
GBIAS (Pin 16):
8V Regulator Output for Boostrapping programmed level is (C • 0.8V)/10µA. VBOOST . A bypass capacitor of at least 2µF is needed.
VFB (Pin 8):
Voltage Amplifier Inverting Input. A resistor
Exposed Pad (Pin 17):
Connect to PGND (Pin 14). divider to this pin sets the output voltage. Nominal voltage at this pin is 0.8V. 3710f 5
U U U PI FU CTIO S BOOST (Pin 1):
Topside (Boosted) Driver Supply. This pin
BGS (Pin 9):
Bottom Gate Switching Control. CA2 moni- is used to bootstrap and supply the topside power switch tors the inductor current and prohibits BGATE from turn- gate drive circuitry. In normal operation VBOOST is powered ing on when the inductor current is low (below 8mV across from the internally generated 8V GBIAS, VBOOST = VSW + the current sense resistor RS1) to allow discontinous 8.2V when TGATE is on. mode operation. Grounding this pin disables comparator CA2.
TGATE (Pin 2):
Topside (Boosted) N-Channel MOSFET Driver. When TGATE is on, the voltage is equal to VSW + 6V.
VAOUT (Pin 10):
Voltage Amplifier Output.
SW (Pin 3):
Switch Node Connection to Inductor.
CL+ (Pin 11):
Current Limit Amplifier Positive Input. The threshold is set at 70mV.
CSET (Pin 4):
Oscillator Timing Pin. The capacitor on this pin sets the PWM switching frequency.
CL– (Pin 12):
Current Limit Amplifier Negative Input. When used, CL– is connected to the output capacitor side
SYNC (Pin 5):
Synchronization Input. This pin should be of the current + sense resistor and CL+ is connected to the connected to the secondary side output of the power inductor side of the current sense resistor. transformer with a series resistor. A filtering capacitor of 10pF is recommended.
VCC (Pin 13):
Supply of the IC. For proper bypassing, a low ESR capacitor is required.
ILCOMP (Pin 6):
Current Limit Amplifier Compensation Node. At current limit, CA1 pulls down on this pin to
PGND (Pin 14):
Ground of the Bottom Side N-Channel regulate the output current. MOSFET Driver.
SS (Pin 7):
Soft-Start. A capacitor on this pin sets the
BGATE (Pin 15):
Bottom Side N-Channel MOSFET Driver. output ramp up rate. The typical time for SS to reach the
GBIAS (Pin 16):
8V Regulator Output for Boostrapping programmed level is (C • 0.8V)/10µA. VBOOST . A bypass capacitor of at least 2µF is needed.
VFB (Pin 8):
Voltage Amplifier Inverting Input. A resistor
Exposed Pad (Pin 17):
Connect to PGND (Pin 14). divider to this pin sets the output voltage. Nominal voltage at this pin is 0.8V. 3710f 5
