Datasheet LTC1698 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Isolated Secondary Synchronous Rectifier Controller |
| Pages / Page | 24 / 7 — PI FU CTIO S VDD (Pin 1):. OVPIN (Pin 9):. CG (Pin 2):. PWRGD (Pin 10):. … |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
PI FU CTIO S VDD (Pin 1):. OVPIN (Pin 9):. CG (Pin 2):. PWRGD (Pin 10):. PGND (Pin 3):. GND (Pin 4):. ISNSGND (Pin 11):
Model Line for this Datasheet
Text Version of Document
LTC1698
U U U PI FU CTIO S VDD (Pin 1):
Power Supply Input. For isolated applica- compensates the feedback loop. If VFB goes low, VCOMP tions, a simple rectifier from the power transformer is pulls high and OPTODRV goes low. used to power the chip. This pin powers the opto driver,
OVPIN (Pin 9):
Overvoltage Input. OVPIN is a high imped- the VAUX supply and the FG and CG drivers. An internal 5V ance input to an internal comparator. The threshold of this regulator powers the remaining circuitry. VDD requires an comparator is set to 1.233V. If the OVPIN potential is external 4.7µF bypass capacitor. higher than the threshold voltage, OPTODRV pulls high
CG (Pin 2):
Catch Gate Driver. If SYNC slews positive, CG immediately. Use an external RC lowpass filter to prevent pulls high to drive an external N-channel MOSFET. CG noisy signals from triggering this comparator. draws power from the VDD pin and swings between VDD
PWRGD (Pin 10):
Power Good Output. This is an open- and PGND. drain output. PWRGD floats if VFB is above 94% of the
PGND (Pin 3):
Power Ground. Connect PGND to a low nominal value for more than 2ms. PWRGD pulls low if VFB impedance ground plane in close proximity to the ground is below 94% of the nominal value for more than 1ms. The terminal of the external current sensing resistor. PWRGD threshold is independent of the MARGIN pin potential.
GND (Pin 4):
Logic and Signal Ground. GND is referenced to the internal low power circuitry. Careful board layout
ISNSGND (Pin 11):
Current Sense Ground. Connect to the techniques must be used to prevent corruption of signal positive side of the sense resistor, normally grounded. ground reference. Connect GND and PGND together di-
I
rectly at the LTC1698.
SNS (Pin 12):
Current Sense Input. Connect to the nega- tive side of the sense resistor through an external RC
OPTODRV (Pin 5):
Optocoupler Driver Output. This pin lowpass filter. This pin normally sees a negative voltage, drives a ground referenced optocoupler through an exter- which is proportional to the average load current. If nal resistor. If VFB is low, OPTODRV pulls low. If VFB is current limit is exceeded, OPTODRV pulls high. high, OPTODRV pulls high. This optocoupler driver has a
I
DC gain of 5. During overvoltage or overcurrent condi-
COMP (Pin 13):
Current Amplifier Output. An RC network at this pin compensates the current limit feedback loop. tions, OPTODRV pulls high. The output is capable of Referencing the RC to V sourcing 10mA of current and will drive an external 0.1µF OUT controls output voltage over- shoot on start-up. This pin can float if current limit loop capacitive load and is short-circuit protected. compensation is not required.
VCOMP (Pin 6):
Error Amplifier Output. This error amplifier
V
is able to drive more than 2kΩ and 100pF of load. The
AUX (Pin 14):
Auxiliary 3.3V Logic Supply. This pin requires a 0.1µF or greater bypass capacitor. This auxiliary internal diode connected from VFB to VCOMP reduces power supply can power external devices and sources OPTODRV recovery time under start-up conditions. 10mA of current. Internal current limiting is provided.
MARGIN (Pin 7):
Current Input to Adjust the Output
SYNC (Pin 15):
Drivers Synchronization Input. A negative Voltage Linearly. The MARGIN pin connects to an internal voltage slew at SYNC forces FG to pull high and CG to pull 16.5k resistor. The other end of this resistor is regulated low. A positive voltage slew at SYNC resets the FG pin and to 1.65V. Connecting MARGIN to a 3.3V logic supply CG pulls high. If SYNC loses its synchronization signal for sources 100µA of current into the chip and moves the more than the driver disable time-out interval, both the output voltage 5% higher. Connecting MARGIN to 0V forward and catch drivers output are forced low. The SYNC sinks 100µA out of the pin and moves the regulated output circuit accepts pulse and square wave signals. The mini- voltage 5% lower. The MARGIN pin voltage does not affect mum pulse width is 75ns. The synchronization frequency the PWRGD and OVPIN trip points. range is between 50kHz to 400kHz.
VFB (Pin 8):
Feedback Voltage. VFB senses the regulated
FG (Pin 16):
Forward Gate Driver. If SYNC slews negative, output voltage through an external resistor divider. The FG goes high. FG draws power from V V DD and swings FB pin is servoed to the reference voltage of 1.233V under between V closed-loop conditions. An RC network from V DD and PGND. FB to VCOMP 1698f 7
U U U PI FU CTIO S VDD (Pin 1):
Power Supply Input. For isolated applica- compensates the feedback loop. If VFB goes low, VCOMP tions, a simple rectifier from the power transformer is pulls high and OPTODRV goes low. used to power the chip. This pin powers the opto driver,
OVPIN (Pin 9):
Overvoltage Input. OVPIN is a high imped- the VAUX supply and the FG and CG drivers. An internal 5V ance input to an internal comparator. The threshold of this regulator powers the remaining circuitry. VDD requires an comparator is set to 1.233V. If the OVPIN potential is external 4.7µF bypass capacitor. higher than the threshold voltage, OPTODRV pulls high
CG (Pin 2):
Catch Gate Driver. If SYNC slews positive, CG immediately. Use an external RC lowpass filter to prevent pulls high to drive an external N-channel MOSFET. CG noisy signals from triggering this comparator. draws power from the VDD pin and swings between VDD
PWRGD (Pin 10):
Power Good Output. This is an open- and PGND. drain output. PWRGD floats if VFB is above 94% of the
PGND (Pin 3):
Power Ground. Connect PGND to a low nominal value for more than 2ms. PWRGD pulls low if VFB impedance ground plane in close proximity to the ground is below 94% of the nominal value for more than 1ms. The terminal of the external current sensing resistor. PWRGD threshold is independent of the MARGIN pin potential.
GND (Pin 4):
Logic and Signal Ground. GND is referenced to the internal low power circuitry. Careful board layout
ISNSGND (Pin 11):
Current Sense Ground. Connect to the techniques must be used to prevent corruption of signal positive side of the sense resistor, normally grounded. ground reference. Connect GND and PGND together di-
I
rectly at the LTC1698.
SNS (Pin 12):
Current Sense Input. Connect to the nega- tive side of the sense resistor through an external RC
OPTODRV (Pin 5):
Optocoupler Driver Output. This pin lowpass filter. This pin normally sees a negative voltage, drives a ground referenced optocoupler through an exter- which is proportional to the average load current. If nal resistor. If VFB is low, OPTODRV pulls low. If VFB is current limit is exceeded, OPTODRV pulls high. high, OPTODRV pulls high. This optocoupler driver has a
I
DC gain of 5. During overvoltage or overcurrent condi-
COMP (Pin 13):
Current Amplifier Output. An RC network at this pin compensates the current limit feedback loop. tions, OPTODRV pulls high. The output is capable of Referencing the RC to V sourcing 10mA of current and will drive an external 0.1µF OUT controls output voltage over- shoot on start-up. This pin can float if current limit loop capacitive load and is short-circuit protected. compensation is not required.
VCOMP (Pin 6):
Error Amplifier Output. This error amplifier
V
is able to drive more than 2kΩ and 100pF of load. The
AUX (Pin 14):
Auxiliary 3.3V Logic Supply. This pin requires a 0.1µF or greater bypass capacitor. This auxiliary internal diode connected from VFB to VCOMP reduces power supply can power external devices and sources OPTODRV recovery time under start-up conditions. 10mA of current. Internal current limiting is provided.
MARGIN (Pin 7):
Current Input to Adjust the Output
SYNC (Pin 15):
Drivers Synchronization Input. A negative Voltage Linearly. The MARGIN pin connects to an internal voltage slew at SYNC forces FG to pull high and CG to pull 16.5k resistor. The other end of this resistor is regulated low. A positive voltage slew at SYNC resets the FG pin and to 1.65V. Connecting MARGIN to a 3.3V logic supply CG pulls high. If SYNC loses its synchronization signal for sources 100µA of current into the chip and moves the more than the driver disable time-out interval, both the output voltage 5% higher. Connecting MARGIN to 0V forward and catch drivers output are forced low. The SYNC sinks 100µA out of the pin and moves the regulated output circuit accepts pulse and square wave signals. The mini- voltage 5% lower. The MARGIN pin voltage does not affect mum pulse width is 75ns. The synchronization frequency the PWRGD and OVPIN trip points. range is between 50kHz to 400kHz.
VFB (Pin 8):
Feedback Voltage. VFB senses the regulated
FG (Pin 16):
Forward Gate Driver. If SYNC slews negative, output voltage through an external resistor divider. The FG goes high. FG draws power from V V DD and swings FB pin is servoed to the reference voltage of 1.233V under between V closed-loop conditions. An RC network from V DD and PGND. FB to VCOMP 1698f 7
