Datasheet AT90S8535, AT90LS8535 (Atmel) - 16

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Figure 20.
The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 System Clock Ø 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 21 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register.
Figure 21.
Single Cycle ALU Operation T1 T2 T3 T4 System Clock Ø Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back The internal data SRAM access is performed in two System Clock cycles as described in Figure 22.
Figure 22.
On-chip Data SRAM Access Cycles T1 T2 T3 T4 System Clock Ø Address Prev. Address Address Data ite WR Wr Data RD Read
16 AT90S/LS8535
1041H–11/01 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Clock Options Crystal Oscillator External Clock Timer Oscillator Architectural Overview General-purpose Register File X-register, Y-register and Z- register ALU – Arithmetic Logic Unit In-System Programmable Flash Program Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd And Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post- increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing I/O Memory Status Register – SREG Stack Pointer – SP Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Watchdog Reset MCU Status Register – MCUSR Interrupt Handling General Interrupt Mask Register – GIMSK General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR External Interrupts Interrupt Response Time MCU Control Register – MCUCR Sleep Modes Idle Mode Power-down Mode Power Save Mode Timer/Counters Timer/Counter Prescalers 8-bit Timer/Counter0 Timer/Counter0 Control Register – TCCR0 Timer Counter 0 – TCNT0 16-bit Timer/Counter1 Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 – TCNT1H AND TCNT1L Timer/Counter1 Output Compare Register – OCR1AH AND OCR1AL Timer/Counter1 Output Compare Register – OCR1BH AND OCR1BL Timer/Counter1 Input Capture Register – ICR1H AND ICR1L Timer/Counter1 In PWM Mode 8-bit Timer/Counter2 Timer/Counter2 Control Register – TCCR2 Timer/Counter2 – TCNT2 Timer/Counter2 Output Compare Register – OCR2 Timer/Counter2 in PWM Mode Asynchronous Status Register – ASSR Asynchronous Operation of Timer/Counter2 Watchdog Timer Watchdog Timer Control Register – WDTCR EEPROM Read/Write Access EEPROM Address Register – EEARH and EEARL EEPROM Data Register – EEDR EEPROM Control Register – EECR Prevent EEPROM Corruption Serial Peripheral Interface – SPI SS Pin Functionality Data Modes SPI Control Register – SPCR SPI Status Register – SPSR SPI Data Register – SPDR UART Data Transmission Data Reception UART Control UART I/O Data Register – UDR UART Status Register – USR UART Control Register – UCR Baud Rate Generator UART Baud Rate Register – UBRR Analog Comparator Analog Comparator Control and Status Register – ACSR Analog-to-Digital Converter Feature list Operation Prescaling ADC Noise Canceler Function ADC Multiplexer Select Register – ADMUX ADC Control and Status Register – ADCSR ADC Data Register – ADCL AND ADCH Scanning Multiple Channels ADC Noise Canceling Techniques ADC Characteristics I/O Ports Port A Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port A as General Digital I/O Port A Schematics Port B Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port B As General Digital I/O Alternate Functions of Port B Port B Schematics Port C Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port C As General Digital I/O Alternate Functions of Port C Port C Schematics Port D Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port D As General Digital I/O Alternate Functions of Port D Port D Schematics Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 44A 44J 40P6 44M1