Datasheet AT90S8535, AT90LS8535 (Atmel) - 5
| Manufacturer | Atmel |
| Description | 8-bit AVR Microcontroller with 8K Bytes In-System Programmable Flash |
| Pages / Page | 127 / 5 — AT90S/LS8535. Port D (PD7..PD0). RESET. XTAL1. XTAL2. AVCC. AREF. AGND |
| File Format / Size | PDF / 2.5 Mb |
| Document Language | English |
AT90S/LS8535. Port D (PD7..PD0). RESET. XTAL1. XTAL2. AVCC. AREF. AGND
Model Line for this Datasheet
Text Version of Document
link to page 86 link to page 68
AT90S/LS8535
current if the pull-up resistors are activated. Two Port C pins can alternatively be used as oscillator for Timer/Counter2. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features of the AT90S8535 as listed on page 86. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
AVCC
AVCC is the supply voltage pin for Port A and the A/D Converter. If the ADC is not used, this pin must be connected to VCC. If the ADC is used, this pin must be connected to VCC via a low-pass filter. See page 68 for details on operation of the ADC.
AREF
AREF is the analog reference input for the A/D Converter. For ADC operations, a volt- age in the range 2V to AVCC must be applied to this pin.
AGND
Analog ground. If the board has a separate analog ground plane, this pin should be con- nected to this ground plane. Otherwise, connect to GND.
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1041H–11/01 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Clock Options Crystal Oscillator External Clock Timer Oscillator Architectural Overview General-purpose Register File X-register, Y-register and Z- register ALU – Arithmetic Logic Unit In-System Programmable Flash Program Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd And Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post- increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing I/O Memory Status Register – SREG Stack Pointer – SP Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Watchdog Reset MCU Status Register – MCUSR Interrupt Handling General Interrupt Mask Register – GIMSK General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR External Interrupts Interrupt Response Time MCU Control Register – MCUCR Sleep Modes Idle Mode Power-down Mode Power Save Mode Timer/Counters Timer/Counter Prescalers 8-bit Timer/Counter0 Timer/Counter0 Control Register – TCCR0 Timer Counter 0 – TCNT0 16-bit Timer/Counter1 Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 – TCNT1H AND TCNT1L Timer/Counter1 Output Compare Register – OCR1AH AND OCR1AL Timer/Counter1 Output Compare Register – OCR1BH AND OCR1BL Timer/Counter1 Input Capture Register – ICR1H AND ICR1L Timer/Counter1 In PWM Mode 8-bit Timer/Counter2 Timer/Counter2 Control Register – TCCR2 Timer/Counter2 – TCNT2 Timer/Counter2 Output Compare Register – OCR2 Timer/Counter2 in PWM Mode Asynchronous Status Register – ASSR Asynchronous Operation of Timer/Counter2 Watchdog Timer Watchdog Timer Control Register – WDTCR EEPROM Read/Write Access EEPROM Address Register – EEARH and EEARL EEPROM Data Register – EEDR EEPROM Control Register – EECR Prevent EEPROM Corruption Serial Peripheral Interface – SPI SS Pin Functionality Data Modes SPI Control Register – SPCR SPI Status Register – SPSR SPI Data Register – SPDR UART Data Transmission Data Reception UART Control UART I/O Data Register – UDR UART Status Register – USR UART Control Register – UCR Baud Rate Generator UART Baud Rate Register – UBRR Analog Comparator Analog Comparator Control and Status Register – ACSR Analog-to-Digital Converter Feature list Operation Prescaling ADC Noise Canceler Function ADC Multiplexer Select Register – ADMUX ADC Control and Status Register – ADCSR ADC Data Register – ADCL AND ADCH Scanning Multiple Channels ADC Noise Canceling Techniques ADC Characteristics I/O Ports Port A Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port A as General Digital I/O Port A Schematics Port B Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port B As General Digital I/O Alternate Functions of Port B Port B Schematics Port C Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port C As General Digital I/O Alternate Functions of Port C Port C Schematics Port D Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port D As General Digital I/O Alternate Functions of Port D Port D Schematics Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 44A 44J 40P6 44M1
AT90S/LS8535
current if the pull-up resistors are activated. Two Port C pins can alternatively be used as oscillator for Timer/Counter2. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features of the AT90S8535 as listed on page 86. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
AVCC
AVCC is the supply voltage pin for Port A and the A/D Converter. If the ADC is not used, this pin must be connected to VCC. If the ADC is used, this pin must be connected to VCC via a low-pass filter. See page 68 for details on operation of the ADC.
AREF
AREF is the analog reference input for the A/D Converter. For ADC operations, a volt- age in the range 2V to AVCC must be applied to this pin.
AGND
Analog ground. If the board has a separate analog ground plane, this pin should be con- nected to this ground plane. Otherwise, connect to GND.
5
1041H–11/01 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Clock Options Crystal Oscillator External Clock Timer Oscillator Architectural Overview General-purpose Register File X-register, Y-register and Z- register ALU – Arithmetic Logic Unit In-System Programmable Flash Program Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd And Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post- increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing I/O Memory Status Register – SREG Stack Pointer – SP Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Watchdog Reset MCU Status Register – MCUSR Interrupt Handling General Interrupt Mask Register – GIMSK General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR External Interrupts Interrupt Response Time MCU Control Register – MCUCR Sleep Modes Idle Mode Power-down Mode Power Save Mode Timer/Counters Timer/Counter Prescalers 8-bit Timer/Counter0 Timer/Counter0 Control Register – TCCR0 Timer Counter 0 – TCNT0 16-bit Timer/Counter1 Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 – TCNT1H AND TCNT1L Timer/Counter1 Output Compare Register – OCR1AH AND OCR1AL Timer/Counter1 Output Compare Register – OCR1BH AND OCR1BL Timer/Counter1 Input Capture Register – ICR1H AND ICR1L Timer/Counter1 In PWM Mode 8-bit Timer/Counter2 Timer/Counter2 Control Register – TCCR2 Timer/Counter2 – TCNT2 Timer/Counter2 Output Compare Register – OCR2 Timer/Counter2 in PWM Mode Asynchronous Status Register – ASSR Asynchronous Operation of Timer/Counter2 Watchdog Timer Watchdog Timer Control Register – WDTCR EEPROM Read/Write Access EEPROM Address Register – EEARH and EEARL EEPROM Data Register – EEDR EEPROM Control Register – EECR Prevent EEPROM Corruption Serial Peripheral Interface – SPI SS Pin Functionality Data Modes SPI Control Register – SPCR SPI Status Register – SPSR SPI Data Register – SPDR UART Data Transmission Data Reception UART Control UART I/O Data Register – UDR UART Status Register – USR UART Control Register – UCR Baud Rate Generator UART Baud Rate Register – UBRR Analog Comparator Analog Comparator Control and Status Register – ACSR Analog-to-Digital Converter Feature list Operation Prescaling ADC Noise Canceler Function ADC Multiplexer Select Register – ADMUX ADC Control and Status Register – ADCSR ADC Data Register – ADCL AND ADCH Scanning Multiple Channels ADC Noise Canceling Techniques ADC Characteristics I/O Ports Port A Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port A as General Digital I/O Port A Schematics Port B Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port B As General Digital I/O Alternate Functions of Port B Port B Schematics Port C Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port C As General Digital I/O Alternate Functions of Port C Port C Schematics Port D Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port D As General Digital I/O Alternate Functions of Port D Port D Schematics Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 44A 44J 40P6 44M1
