Datasheet AT90S1200 (Atmel) - 6

link to page 6 link to page 37 During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is a 3-level-deep hardware stack dedicated for subrou- tines and interrupts. The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, A/D Converters and other I/O functions. The mem- ory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a sepa- r a t e i n t e r r u p t v e c t o r i n t h e i n t e r r u p t v e c t o r t a b l e a t t h e b e g i n n i n g o f t h e program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.
General Purpose
Figure 5 shows the structure of the 32 general purpose registers in the CPU.
Register File Figure 5.
AVR CPU General Purpose Working Registers 7 0 R0 R1 R2 General … Purpose … Working R28 Registers R29 R30 (Z-Register) R31 All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND, OR and all other operations between two registers or on a single register apply to the entire register file. Register 30 also serves as an 8-bit pointer for indirect address of the register file.
ALU – Arithmetic Logic
The high-performance AVR ALU operates in direct connection with all the 32 general
Unit
purpose working registers. Within a single clock cycle, ALU operations between regis- ters in the register file are executed. The ALU operations are divided into three main categories – arithmetic, logic and bit-functions.
In-System
The AT90S1200 contains 1K bytes On-chip In-System Programmable Flash memory for
Programmable Flash
program storage. Since all instructions are single 16-bit words, the Flash is organized as
Program Memory
512 x 16. The Flash memory has an endurance of at least 1000 write/erase cycles. The AT90S1200 Program Counter is 9 bits wide, thus addressing the 512 words Flash program memory. See page 37 for a detailed description on Flash data downloading.
6 AT90S1200
0838H–AVR–03/02 Document Outline Features Pin Configuration Description Block Diagram Pin Descriptions VCC GND Port B (PB7..PB0) Port D (PD6..PD0) RESET XTAL1 XTAL2 Crystal Oscillator On-chip RC Oscillator Architectural Overview General Purpose Register File ALU – Arithmetic Logic Unit In-System Programmable Flash Program Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Subroutine and Interrupt Hardware Stack EEPROM Data Memory Instruction Execution Timing I/O Memory Status Register – SREG Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Watchdog Reset Interrupt Handling General Interrupt Mask Register – GIMSK Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt FLAG Register – TIFR External Interrupts Interrupt Response Time MCU Control Register – MCUCR Sleep Modes Idle Mode Power-down Mode Timer/Counter0 Timer/Counter0 Prescaler Timer/Counter0 Control Register – TCCR0 Timer/Counter0 – TCNT0 Watchdog Timer Watchdog Timer Control Register – WDTCR EEPROM Read/Write Access EEPROM Address Register – EEAR EEPROM Data Register – EEDR EEPROM Control Register – EECR Prevent EEPROM Corruption Analog Comparator Analog Comparator Control and Status Register – ACSR I/O Ports Port B Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pin Address – PINB Port B as General Digital I/O Alternate Functions of Port B Port B Schematics Port D Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port D as General Digital I/O Alternate Functions for Port D Port D Schematics Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Clock Drive Typical Characteristics AT90S1200 Register Summary Instruction Set Summary Ordering Information(1) Packaging Information 20P3 20S 20Y Table of Contents