Datasheet ADM3260 (Analog Devices) - 6

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ADM3260 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Side 2 to Side 1 Rising Edge3 tPLH21 31 70 ns Falling Edge4 tPHL21 85 155 ns 3 V Operation 3.0 V ≤ VDDISO, VDDP ≤ 3.6 V, CL1 = CL2 = 0 pF, R1 = 1.0 kΩ, R2 = 120 Ω Side 1 to Side 2 Rising Edge1 tPLH12 82 125 ns Falling Edge2 tPHL12 196 340 ns Side 2 to Side 1 Rising Edge3 tPLH21 32 75 ns Falling Edge4 tPHL21 110 210 ns PULSE WIDTH DISTORTION 5 V Operation 4.5 V ≤ VDDISO, VDDP ≤ 5.5 V, CL1 = CL2 = 0 pF, R1 = 1.6 kΩ, R2 = 180 Ω Side 1 to Side 2, |tPLH12 − tPHL12| PWD12 67 145 ns Side 2 to Side 1, |tPLH21 − tPHL21| PWD21 54 85 ns 3 V Operation 3.0 V ≤ VDDISO, VDDP ≤ 3.6 V, CL1 = CL2 = 0 pF, R1 = 1.0 kΩ, R2 = 120 Ω Side 1 to Side 2, |tPLH12 − tPHL12| PWD12 114 215 ns Side 2 to Side 1, |tPLH21 − tPHL21| PWD21 77 135 ns COMMON-MODE TRANSIENT IMMUNITY5 |CMH|, |CML| 25 35 kV/µs 1 tPLH12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 VDDP. 2 tPHL12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V. 3 tPLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 VDDISO. 4 tPHL21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V. 5 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDP. |CML| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
PACKAGE CHARACTERISTICS Table 8. Thermal and Isolation Characteristics Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1 RI-O 1012 Ω Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz Input Capacitance2 CI 4.0 pF IC Junction-to-Ambient Thermal Resistance θJA 50 °C/W Thermocouple located at center of package underside, test conducted on 4-layer board with thin traces3 1 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together; and Pin 11 through Pin 20 are shorted together. 2 Input capacitance is from any input data pin to ground. 3 See the Thermal Analysis section for thermal model definitions. Rev. D | Page 6 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY DC-TO-DC CONVERTER CHARACTERISTICS DIGITAL ISOLATOR DC SPECIFICATIONS DIGITAL ISOLATOR AC SPECIFICATIONS PACKAGE CHARACTERISTICS REGULATORY APPROVALS INSULATION AND SAFETY RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION VISO VOLTAGE TRUTH TABLE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CONDITION APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION DIGITAL ISOLATOR STARTUP TYPICAL APPLICATION DIAGRAM PCB LAYOUT THERMAL ANALYSIS EMI CONSIDERATIONS INSULATION LIFETIME APPLICATIONS EXAMPLE OUTLINE DIMENSIONS ORDERING GUIDE