Datasheet LT1236LS8 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Precision, Low Noise, Low Profile Hermetic Voltage Reference |
| Pages / Page | 16 / 7 — applicaTions inForMaTion Effect of Reference Drift on System Accuracy. … |
| File Format / Size | PDF / 233 Kb |
| Document Language | English |
applicaTions inForMaTion Effect of Reference Drift on System Accuracy. Capacitive Loading and Transient Response
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LT1236LS8
applicaTions inForMaTion Effect of Reference Drift on System Accuracy
A large portion of the temperature drift error budget in LT1236LS8 IN V many systems is the system reference voltage. This graph OUT OUT GND TRIM R1 indicates the maximum temperature coefficient allowable 27k R2 if the reference is to contribute no more than 0.5LSB error 50k 1N4148 to the overall system performance. The example shown is a 12-bit system designed to operate over a temperature range from 25°C to 65°C. Assuming the system calibration 1236ls8 AI02 is performed at 25°C, the temperature span is 40°C. It can
Capacitive Loading and Transient Response
be seen from the graph that the temperature coefficient of the reference must be no worse than 3ppm/°C if it is The LT1236LS8 is stable with all capacitive loads, but for to contribute less than 0.5LSB error. For this reason, the optimum settling with load transients, output capacitance LT1236LS8 has been optimized for low drift. should be under 1000pF. The output stage of the reference is class AB with a fairly low idling current. This makes
Maximum Allowable Reference Drift
transient response worst-case at light load currents. Because of internal current drain on the output, actual 100 worst-case occurs at ILOAD = 0. Significantly better load 8-BIT transient response is obtained by moving slightly away from these points. See Load Transient Response curves 10-BIT for details. In general, best transient response is obtained 10 when the output is sourcing current. In critical applica- tions, a 10µF solid tantalum capacitor with several ohms 12-BIT in series provides optimum output bypass. 0.5LSB ERROR (ppm/°C) 14-BIT
Load Regulation
MAXIMUM TEMPERATURE COEFFICIENT FOR 1.0 10 20 30 40 50 60 70 80 90 100 The LT1236LS8 is capable of driving 10mA to a load. The TEMPERATURE SPAN (°C) 1236ls8 AI01 load regulation at the output of the LT1236LS8 is very good, with a change of less than 25ppm/mA when driving
Trimming Output Voltage
the load. However, the load current will cause a voltage The LT1236LS8 has an output voltage trim pin, but the drop in the connecting wire between the LT1236LS8 and temperature drift of the nominal 4V open circuit voltage the load. This IR drop is dependent on the resistance of at pin 5 is about –1.7mV/°C. For the voltage trimming not the connecting wire and will appear as additional load to affect reference output temperature drift, the external regulation error. For example, 12 feet of #22 gauge wire or trim voltage must track the voltage on the trim pin. Input 1 foot of 0.025 inch printed circuit board trace will create impedance of the trim pin is about 100kΩ and attenua- 2mV loss at 10mA output current. This is equivalent to tion to the output is 13:1. The technique shown below 1LSB in a 10V, 12-bit system. is suggested for trimming the output of the LT1236LS8 There are three approaches that wil reduce this effect. First, while maintaining minimum shift in output temperature limiting the distance between the LT1236LS8 and the load coefficient. The R1/R2 ratio is chosen to minimize interac- will reduce the trace length, and improve load regulation. tion of trimming and temperature drift shifts, so the exact Second, use wider traces for the connections between values shown should be used. the LT1236LS8 and the load to reduce IR drop. Finally, 1236ls8f 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
applicaTions inForMaTion Effect of Reference Drift on System Accuracy
A large portion of the temperature drift error budget in LT1236LS8 IN V many systems is the system reference voltage. This graph OUT OUT GND TRIM R1 indicates the maximum temperature coefficient allowable 27k R2 if the reference is to contribute no more than 0.5LSB error 50k 1N4148 to the overall system performance. The example shown is a 12-bit system designed to operate over a temperature range from 25°C to 65°C. Assuming the system calibration 1236ls8 AI02 is performed at 25°C, the temperature span is 40°C. It can
Capacitive Loading and Transient Response
be seen from the graph that the temperature coefficient of the reference must be no worse than 3ppm/°C if it is The LT1236LS8 is stable with all capacitive loads, but for to contribute less than 0.5LSB error. For this reason, the optimum settling with load transients, output capacitance LT1236LS8 has been optimized for low drift. should be under 1000pF. The output stage of the reference is class AB with a fairly low idling current. This makes
Maximum Allowable Reference Drift
transient response worst-case at light load currents. Because of internal current drain on the output, actual 100 worst-case occurs at ILOAD = 0. Significantly better load 8-BIT transient response is obtained by moving slightly away from these points. See Load Transient Response curves 10-BIT for details. In general, best transient response is obtained 10 when the output is sourcing current. In critical applica- tions, a 10µF solid tantalum capacitor with several ohms 12-BIT in series provides optimum output bypass. 0.5LSB ERROR (ppm/°C) 14-BIT
Load Regulation
MAXIMUM TEMPERATURE COEFFICIENT FOR 1.0 10 20 30 40 50 60 70 80 90 100 The LT1236LS8 is capable of driving 10mA to a load. The TEMPERATURE SPAN (°C) 1236ls8 AI01 load regulation at the output of the LT1236LS8 is very good, with a change of less than 25ppm/mA when driving
Trimming Output Voltage
the load. However, the load current will cause a voltage The LT1236LS8 has an output voltage trim pin, but the drop in the connecting wire between the LT1236LS8 and temperature drift of the nominal 4V open circuit voltage the load. This IR drop is dependent on the resistance of at pin 5 is about –1.7mV/°C. For the voltage trimming not the connecting wire and will appear as additional load to affect reference output temperature drift, the external regulation error. For example, 12 feet of #22 gauge wire or trim voltage must track the voltage on the trim pin. Input 1 foot of 0.025 inch printed circuit board trace will create impedance of the trim pin is about 100kΩ and attenua- 2mV loss at 10mA output current. This is equivalent to tion to the output is 13:1. The technique shown below 1LSB in a 10V, 12-bit system. is suggested for trimming the output of the LT1236LS8 There are three approaches that wil reduce this effect. First, while maintaining minimum shift in output temperature limiting the distance between the LT1236LS8 and the load coefficient. The R1/R2 ratio is chosen to minimize interac- will reduce the trace length, and improve load regulation. tion of trimming and temperature drift shifts, so the exact Second, use wider traces for the connections between values shown should be used. the LT1236LS8 and the load to reduce IR drop. Finally, 1236ls8f 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
