Datasheet LTM4636-1 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 40A μModule Regulator with Overvoltage/ Overtemperature Protection |
| Pages / Page | 38 / 9 — HIZREG (F3):. OVER_TEMP (D10):. OVP_SET (E12):. BIAS (G9):. TEMP+ (G12):. … |
| File Format / Size | PDF / 2.3 Mb |
| Document Language | English |
HIZREG (F3):. OVER_TEMP (D10):. OVP_SET (E12):. BIAS (G9):. TEMP+ (G12):. SGND (F4, G4):. OTP_SET (F11):. INTVCC (F6):. TEMP– (G11):
Model Line for this Datasheet
Text Version of Document
LTM4636-1 PIN FUNCTIONS
HIZREG (F3):
When this pin is pulled low the power stage and PVCC together. Then tie RUNP to GND. If VIN > 5.5V is disabled into high impedance. Tie this pin to VIN or then operate PVCC regulator as normal. See the Typical INTVCC for normal operation. Application examples.
OVER_TEMP (D10):
This overtemperature protection is
OVP_SET (E12):
This pin is used to set the output overvolt- programmable with an internal monitor that is referenced age trip point. This pin has a 24.9kΩ resistor on it to ground. to the TMON pin and the OTP_SET pin. The OVER_TEMP See the Applications Information section. Float is not used. pin can be used to alert the system if the module regulator
BIAS (G9):
This pin is used to power the OTP and OVP overheats, and this signal can be used to trip off and retry circuitry independently of the main power feed. See the an electronic circuit breaker in a fault condition. The pin Applications Information section. is an open collector that pulls active low in response to OVER_TEMP. The OVER_TEMP pin can be left floating if not
TEMP+ (G12):
Temperature Monitor. An internal diode used. See the Applications Information section for details. connected NPN transistor. See the Applications Informa- tion section.
SGND (F4, G4):
Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection
OTP_SET (F11):
This pin is used to set the overtemperature to the output capacitor GND in the application. See layout set point. The pin has a 24.9k resistor on it to ground. guidelines in Figure 18. See Applications Information section. Float if not used.
INTVCC (F6):
Internal 5.5V LDO for Driving the Control
TEMP– (G11):
Low Side of the Internal Temperature Circuitry in the LTM4636-1. INTVCC is controlled and Monitor. enabled when RUNC is activated high.
CLKOUT (G3):
Clock out signal that can be phase selected
FREQ (G5):
A resistor can be applied from this pin to to the main internal clock or synchronized clock using ground to set the operating frequency. This pin sources the PHASMD pin. CLKOUT can be used for multiphase 20µA. See the Applications Information section. applications. See the Applications Information section.
PHMODE (G7):
This pin can be voltage programmed to
TEST1 (H4), TEST2 (F5), TEST3 (H2), GMON (H9):
These change the phase relationship of the CLKOUT pin with refer- are test pins used in the final production test of the part. ence to the internal clock or an input synchronized clock. Leave floating. The INTVCC (5.5V) output can be voltage divided down to
V
the PHASMD pin to set the particular phase. The Electri-
IN (H5-H6, J4-J7, K4-K8, L4-L8, M4-M8):
Power Input Pins. Apply input voltage between these pins and GND cal Characteristics show the different settings to select a pins. Recommend placing input decoupling capacitance particular phase. See the Applications Information section. directly between VIN and GND pins.
RUNP (G8):
This pin enables the PVCC supply. This pin
PWM (H7):
PWM output that drives the power stage. Primar- can be connected to VIN, or tie to ground when connecting ily used for test, but can be monitored in debug or testing. PVCC to VIN ≤ 5.5V. RUNP needs to sequence up before RUNC. A 15k resistor from PV
TMON (H8):
Temperature Monitor Pin. Internal temperature CC to RUNC with a 0.1µF capacitor will provide enough delay. In parallel operation monitor, varies from 1.0V at 25°C to 1.44V at 150°C, disables with multiple LTM4636-1s, the resistor can be reduced in power stage at >150°C. The OTP_Trip signal is set to trip value by N times and the 0.1µF can be increased N times. off at a value lower than 150°C. If the temperature moni- See Applications Information section. RUNP can be used to tor feature is not desired, then tie the TMON pin to GND. set the minimum UVLO with a voltage divider. See Figure 1.
SW (L11, K11):
These are pin connections to the internal
PV
switch node for test evaluation and monitoring. An R-C
CC (F9):
5V Power Output and Power for Internal Power MOSFET Drivers. The regulator can power 50mA of external snubber can be placed from the switch pins to GND to sourcing for additional use. Place a 22µF ceramic filter eliminate any high frequency ringing. See the Applications capacitor on this pin to ground. When V Information section. IN < 5.5V, tie VIN 46361fa For more information www.linear.com/LTM4636-1 9
HIZREG (F3):
When this pin is pulled low the power stage and PVCC together. Then tie RUNP to GND. If VIN > 5.5V is disabled into high impedance. Tie this pin to VIN or then operate PVCC regulator as normal. See the Typical INTVCC for normal operation. Application examples.
OVER_TEMP (D10):
This overtemperature protection is
OVP_SET (E12):
This pin is used to set the output overvolt- programmable with an internal monitor that is referenced age trip point. This pin has a 24.9kΩ resistor on it to ground. to the TMON pin and the OTP_SET pin. The OVER_TEMP See the Applications Information section. Float is not used. pin can be used to alert the system if the module regulator
BIAS (G9):
This pin is used to power the OTP and OVP overheats, and this signal can be used to trip off and retry circuitry independently of the main power feed. See the an electronic circuit breaker in a fault condition. The pin Applications Information section. is an open collector that pulls active low in response to OVER_TEMP. The OVER_TEMP pin can be left floating if not
TEMP+ (G12):
Temperature Monitor. An internal diode used. See the Applications Information section for details. connected NPN transistor. See the Applications Informa- tion section.
SGND (F4, G4):
Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection
OTP_SET (F11):
This pin is used to set the overtemperature to the output capacitor GND in the application. See layout set point. The pin has a 24.9k resistor on it to ground. guidelines in Figure 18. See Applications Information section. Float if not used.
INTVCC (F6):
Internal 5.5V LDO for Driving the Control
TEMP– (G11):
Low Side of the Internal Temperature Circuitry in the LTM4636-1. INTVCC is controlled and Monitor. enabled when RUNC is activated high.
CLKOUT (G3):
Clock out signal that can be phase selected
FREQ (G5):
A resistor can be applied from this pin to to the main internal clock or synchronized clock using ground to set the operating frequency. This pin sources the PHASMD pin. CLKOUT can be used for multiphase 20µA. See the Applications Information section. applications. See the Applications Information section.
PHMODE (G7):
This pin can be voltage programmed to
TEST1 (H4), TEST2 (F5), TEST3 (H2), GMON (H9):
These change the phase relationship of the CLKOUT pin with refer- are test pins used in the final production test of the part. ence to the internal clock or an input synchronized clock. Leave floating. The INTVCC (5.5V) output can be voltage divided down to
V
the PHASMD pin to set the particular phase. The Electri-
IN (H5-H6, J4-J7, K4-K8, L4-L8, M4-M8):
Power Input Pins. Apply input voltage between these pins and GND cal Characteristics show the different settings to select a pins. Recommend placing input decoupling capacitance particular phase. See the Applications Information section. directly between VIN and GND pins.
RUNP (G8):
This pin enables the PVCC supply. This pin
PWM (H7):
PWM output that drives the power stage. Primar- can be connected to VIN, or tie to ground when connecting ily used for test, but can be monitored in debug or testing. PVCC to VIN ≤ 5.5V. RUNP needs to sequence up before RUNC. A 15k resistor from PV
TMON (H8):
Temperature Monitor Pin. Internal temperature CC to RUNC with a 0.1µF capacitor will provide enough delay. In parallel operation monitor, varies from 1.0V at 25°C to 1.44V at 150°C, disables with multiple LTM4636-1s, the resistor can be reduced in power stage at >150°C. The OTP_Trip signal is set to trip value by N times and the 0.1µF can be increased N times. off at a value lower than 150°C. If the temperature moni- See Applications Information section. RUNP can be used to tor feature is not desired, then tie the TMON pin to GND. set the minimum UVLO with a voltage divider. See Figure 1.
SW (L11, K11):
These are pin connections to the internal
PV
switch node for test evaluation and monitoring. An R-C
CC (F9):
5V Power Output and Power for Internal Power MOSFET Drivers. The regulator can power 50mA of external snubber can be placed from the switch pins to GND to sourcing for additional use. Place a 22µF ceramic filter eliminate any high frequency ringing. See the Applications capacitor on this pin to ground. When V Information section. IN < 5.5V, tie VIN 46361fa For more information www.linear.com/LTM4636-1 9
