Datasheet LTM4619 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Dual, 26VIN, 4A DC/DC µModule Regulator |
| Pages / Page | 26 / 6 — pin FuncTions. PACKAGE ROW AND COLUMN LABELING MAY VARY. FREQ/PLLFLTR … |
| File Format / Size | PDF / 570 Kb |
| Document Language | English |
pin FuncTions. PACKAGE ROW AND COLUMN LABELING MAY VARY. FREQ/PLLFLTR (J8):. AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
Model Line for this Datasheet
Text Version of Document
LTM4619
pin FuncTions PACKAGE ROW AND COLUMN LABELING MAY VARY FREQ/PLLFLTR (J8):
Frequency Selection Pin. An internal
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
lowpass filter is tied to this pin. The frequency can be
LAYOUT CAREFULLY.
selected from 250kHz to 780kHz by varying the DC volt-
VIN (J1 to J3, J10 to J12, K1 to K4, K9 to K12, L1 to L5,
age on this pin from 0V to 2.4V. The nominal frequency
L8 to L12, M1 to M12):
Power Input Pins. Apply input setting is 500kHz. Frequency selection can be modified as voltage between these pins and PGND pins. Recommend long as the inductor ripple current is less ≈40% to 50% placing input decoupling capacitance directly between VIN at the output current pins and PGND pins. For VIN < 5.5, tie VIN and INTVCC together. 1 V 1– OUT FREQ V VOUT
V
IN
OUT1, VOUT2 (A10 to D10, A11 to D11, A12 to D12, A1 to
IRIPPLE =
D1, A2 to D2, A3 to D3):
Power Output Pins. Apply output L load between these pins and PGND pins. Recommend Where FREQ is selected operating frequency and L is placing output decoupling capacitance directly between the inductor value. Leave this pin floating when external these pins and PGND pins. synchronization is used.
PGND (H1, H2, H4, H9, H11, H12, G1 to G12, F1 to F5, TK/SS1, TK/SS2 (K8, K5):
Output Voltage Tracking and
F7 to F12, E1 to E12, D4 to D9, C4 to C9, B4 to B9, A4 to
Soft-Start Pins. Internal soft-start currents of 1.3µA charge
A9):
Power ground pins for both input and output returns. the soft-start capacitors. See the Applications Information
INTV
section to use the tracking function.
CC (F6):
Internal 5V Regulator Output. This pin is for additional decoupling of the 5V internal regulator.
VFB1, VFB2 (K7, K6):
The negative input of the error
EXTV
amplifier. Internally, this pin is connected to V
CC (J4):
External Power Input to Controller. When OUT with EXTV a 60.4k precision resistor. Different output voltages can CC is higher than 4.7V, the internal 5V regulator is disabled and external power supplies current to reduce be programmed with an additional resistor between VFB the power dissipation in the module. This will improve the and SGND pins. See the Applications Information section efficiency more at high input voltages. for details.
SGND (J6, J7, H6, H7):
Signal Ground Pin. Return ground
COMP1, COMP2 (L7, L6
): Current Control Threshold and path for all analog and low power circuitry. Tie a single Error Amplifier Compensation Point. The module has been connection to PGND in the application. internally compensated for most I/O ranges.
MODE/PLLIN (H8):
Mode selection or external synchroniza-
PGOOD (H5):
Output Voltage Power Good Indicator. Open tion pin. Tying this pin high enables pulse-skipping mode. drain logic output that is pulled to ground when the output Tying this pin low enables force continuous operation. voltage is not within ±7.5% of the regulation point. Floating this pin enables Burst Mode operation. A clock
RUN1, RUN2 (J9, J5):
Run Control Pins. 0.5µA pull-up on the pin will force the controller into the continuous currents on these pins turn on the module if these pins mode of operation and synchronize the internal oscillator. are floating. Forcing either of these pins below 1.2V will The suitable synchronizable frequency range is 250kHz to shut down the corresponding outputs. An additional 4.5µA 780kHz subject to inductor ripple current limits described pull-up current is added to this pin, once the RUN pin rises in the FREQ/PLLFLTR pin section. The external clock input above 1.2V. Also, active control or pull-up resistors can high threshold is 1.6V, while the input low threshold is 1V. be used to enable the RUN pin. The maximum voltage is 6V on these pins.
SW1, SW2 (H10, H3):
Switching Test Pins. These pins are provided externally to check the operation frequency. 4619fc 6 For more information www.linear.com/LTM4619 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Decoupling Requirements Operation Applications Information Typical Applications Package Description Revision History Package Photograph Related Parts Design Resources
pin FuncTions PACKAGE ROW AND COLUMN LABELING MAY VARY FREQ/PLLFLTR (J8):
Frequency Selection Pin. An internal
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
lowpass filter is tied to this pin. The frequency can be
LAYOUT CAREFULLY.
selected from 250kHz to 780kHz by varying the DC volt-
VIN (J1 to J3, J10 to J12, K1 to K4, K9 to K12, L1 to L5,
age on this pin from 0V to 2.4V. The nominal frequency
L8 to L12, M1 to M12):
Power Input Pins. Apply input setting is 500kHz. Frequency selection can be modified as voltage between these pins and PGND pins. Recommend long as the inductor ripple current is less ≈40% to 50% placing input decoupling capacitance directly between VIN at the output current pins and PGND pins. For VIN < 5.5, tie VIN and INTVCC together. 1 V 1– OUT FREQ V VOUT
V
IN
OUT1, VOUT2 (A10 to D10, A11 to D11, A12 to D12, A1 to
IRIPPLE =
D1, A2 to D2, A3 to D3):
Power Output Pins. Apply output L load between these pins and PGND pins. Recommend Where FREQ is selected operating frequency and L is placing output decoupling capacitance directly between the inductor value. Leave this pin floating when external these pins and PGND pins. synchronization is used.
PGND (H1, H2, H4, H9, H11, H12, G1 to G12, F1 to F5, TK/SS1, TK/SS2 (K8, K5):
Output Voltage Tracking and
F7 to F12, E1 to E12, D4 to D9, C4 to C9, B4 to B9, A4 to
Soft-Start Pins. Internal soft-start currents of 1.3µA charge
A9):
Power ground pins for both input and output returns. the soft-start capacitors. See the Applications Information
INTV
section to use the tracking function.
CC (F6):
Internal 5V Regulator Output. This pin is for additional decoupling of the 5V internal regulator.
VFB1, VFB2 (K7, K6):
The negative input of the error
EXTV
amplifier. Internally, this pin is connected to V
CC (J4):
External Power Input to Controller. When OUT with EXTV a 60.4k precision resistor. Different output voltages can CC is higher than 4.7V, the internal 5V regulator is disabled and external power supplies current to reduce be programmed with an additional resistor between VFB the power dissipation in the module. This will improve the and SGND pins. See the Applications Information section efficiency more at high input voltages. for details.
SGND (J6, J7, H6, H7):
Signal Ground Pin. Return ground
COMP1, COMP2 (L7, L6
): Current Control Threshold and path for all analog and low power circuitry. Tie a single Error Amplifier Compensation Point. The module has been connection to PGND in the application. internally compensated for most I/O ranges.
MODE/PLLIN (H8):
Mode selection or external synchroniza-
PGOOD (H5):
Output Voltage Power Good Indicator. Open tion pin. Tying this pin high enables pulse-skipping mode. drain logic output that is pulled to ground when the output Tying this pin low enables force continuous operation. voltage is not within ±7.5% of the regulation point. Floating this pin enables Burst Mode operation. A clock
RUN1, RUN2 (J9, J5):
Run Control Pins. 0.5µA pull-up on the pin will force the controller into the continuous currents on these pins turn on the module if these pins mode of operation and synchronize the internal oscillator. are floating. Forcing either of these pins below 1.2V will The suitable synchronizable frequency range is 250kHz to shut down the corresponding outputs. An additional 4.5µA 780kHz subject to inductor ripple current limits described pull-up current is added to this pin, once the RUN pin rises in the FREQ/PLLFLTR pin section. The external clock input above 1.2V. Also, active control or pull-up resistors can high threshold is 1.6V, while the input low threshold is 1V. be used to enable the RUN pin. The maximum voltage is 6V on these pins.
SW1, SW2 (H10, H3):
Switching Test Pins. These pins are provided externally to check the operation frequency. 4619fc 6 For more information www.linear.com/LTM4619 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Decoupling Requirements Operation Applications Information Typical Applications Package Description Revision History Package Photograph Related Parts Design Resources
