Datasheet LTM4601AHV (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 12A, 28VIN DC/DC µModule Regualtor with PLL, Output Tracking and Margining |
| Pages / Page | 30 / 7 — pin FuncTions (See Package Description for Pin Assignment) VIN (Bank 1):. … |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
pin FuncTions (See Package Description for Pin Assignment) VIN (Bank 1):. TRACK/SS (Pin A9):. OUT (Bank 3):. PGND (Bank 2):
Model Line for this Datasheet
Text Version of Document
LTM4601AHV
pin FuncTions (See Package Description for Pin Assignment) VIN (Bank 1):
Power Input Pins. Apply input voltage be-
TRACK/SS (Pin A9):
Output Voltage Tracking and Soft- Start tween these pins and PGND pins. Recommend placing Pin. When the module is configured as a master output, input decoupling capacitance directly between VIN pins then a soft-start capacitor is placed on this pin to ground to and PGND pins. control the master ramp rate. A soft-start capacitor can be
V
used for soft-start turn on as a stand alone regulator. Slave
OUT (Bank 3):
Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing operation is performed by putting a resistor divider from output decoupling capacitance directly between these pins the master output to ground, and connecting the center and PGND pins. See Figure 17. point of the divider to this pin. See Applications Information.
PGND (Bank 2):
Power ground pins for both input and
MPGM (Pins A12, B11):
Programmable Margining Input. output returns. A resistor from this pin to ground sets a current that is equal to 1.18V/R. This current multiplied by 10kΩ will
V – OSNS (Pin M12):
(–) Input to the Remote Sense Ampli- equal a value in millivolts that is a percentage of the 0.6V fier. This pin connects to the ground remote sense point. reference voltage. See Applications Information. To parallel The remote sense amplifier is used for VOUT ≤3.3V. Tie to LTM4601AHVs, each requires an individual MPGM resistor. INTVCC if not used. Do not tie MPGM pins together. Both pins are internally
V + OSNS (Pin J12):
(+) Input to the Remote Sense Ampli- connected. Pin A12 is a test pin. fier. This pin connects to the output remote sense point.
fSET (Pins B12, C11):
Frequency Set Internally to 850kHz. The remote sense amplifier is used for VOUT ≤3.3V. Tie to An external resistor can be placed from this pin to ground GND if not used. to increase frequency. See Applications Information for
DIFFVOUT (Pin K12):
Output of the Remote Sense Ampli- frequency adjustment. Both pins are internally connected. fier. This pin connects to the VOUT_LCL pin. Leave floating Pin B12 is a test pin. if remote sense amplifier is not used.
VFB (Pin F12):
The Negative Input of the Error Amplifier.
DRVCC (Pin E12):
This pin normally connects to INTVCC Internally, this pin is connected to VOUT_LCL pin with a for powering the internal MOSFET drivers. This pin can 60.4k precision resistor. Different output voltages can be be biased up to 6V from an external supply with about programmed with an additional resistor between VFB and 50mA capability, or an external circuit shown in Figure 18. SGND pins. See Applications Information. This improves efficiency at the higher input voltages by
MARG0 (Pin C12):
This pin is the LSB logic input for the reducing power dissipation in the module. margining function. Together with the MARG1 pin it will
INTVCC (Pin A7, D9):
This pin is for additional decoupling determine if margin high, margin low or no margin state of the 5V internal regulator. These pins are internally con- is applied. The pin has an internal pull-down resistor of nected. Pin A7 is a test pin. 50k. See Applications Information.
PLLIN (Pin A8):
External Clock Synchronization Input to
MARG1 (Pin D12):
This pin is the MSB logic input for the the Phase Detector. This pin is internally terminated to margining function. Together with the MARG0 pin it will SGND with a 50k resistor. Apply a clock with high level determine if margin high, margin low or no margin state above 2V and below INTVCC. See Applications Information. is applied. The pin has an internal pull-down resistor of 50k. See Applications Information.
SGND (Pins H12, H11, G11):
Signal Ground. These pins connect to PGND at output capacitor point. See Figure 17. 4601ahvfc For more information www.linear.com/LTM4601AHV 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Decoupling Requirements Operation Applications Information Typical Applications Package Description Revision History Package Photos Related Parts
pin FuncTions (See Package Description for Pin Assignment) VIN (Bank 1):
Power Input Pins. Apply input voltage be-
TRACK/SS (Pin A9):
Output Voltage Tracking and Soft- Start tween these pins and PGND pins. Recommend placing Pin. When the module is configured as a master output, input decoupling capacitance directly between VIN pins then a soft-start capacitor is placed on this pin to ground to and PGND pins. control the master ramp rate. A soft-start capacitor can be
V
used for soft-start turn on as a stand alone regulator. Slave
OUT (Bank 3):
Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing operation is performed by putting a resistor divider from output decoupling capacitance directly between these pins the master output to ground, and connecting the center and PGND pins. See Figure 17. point of the divider to this pin. See Applications Information.
PGND (Bank 2):
Power ground pins for both input and
MPGM (Pins A12, B11):
Programmable Margining Input. output returns. A resistor from this pin to ground sets a current that is equal to 1.18V/R. This current multiplied by 10kΩ will
V – OSNS (Pin M12):
(–) Input to the Remote Sense Ampli- equal a value in millivolts that is a percentage of the 0.6V fier. This pin connects to the ground remote sense point. reference voltage. See Applications Information. To parallel The remote sense amplifier is used for VOUT ≤3.3V. Tie to LTM4601AHVs, each requires an individual MPGM resistor. INTVCC if not used. Do not tie MPGM pins together. Both pins are internally
V + OSNS (Pin J12):
(+) Input to the Remote Sense Ampli- connected. Pin A12 is a test pin. fier. This pin connects to the output remote sense point.
fSET (Pins B12, C11):
Frequency Set Internally to 850kHz. The remote sense amplifier is used for VOUT ≤3.3V. Tie to An external resistor can be placed from this pin to ground GND if not used. to increase frequency. See Applications Information for
DIFFVOUT (Pin K12):
Output of the Remote Sense Ampli- frequency adjustment. Both pins are internally connected. fier. This pin connects to the VOUT_LCL pin. Leave floating Pin B12 is a test pin. if remote sense amplifier is not used.
VFB (Pin F12):
The Negative Input of the Error Amplifier.
DRVCC (Pin E12):
This pin normally connects to INTVCC Internally, this pin is connected to VOUT_LCL pin with a for powering the internal MOSFET drivers. This pin can 60.4k precision resistor. Different output voltages can be be biased up to 6V from an external supply with about programmed with an additional resistor between VFB and 50mA capability, or an external circuit shown in Figure 18. SGND pins. See Applications Information. This improves efficiency at the higher input voltages by
MARG0 (Pin C12):
This pin is the LSB logic input for the reducing power dissipation in the module. margining function. Together with the MARG1 pin it will
INTVCC (Pin A7, D9):
This pin is for additional decoupling determine if margin high, margin low or no margin state of the 5V internal regulator. These pins are internally con- is applied. The pin has an internal pull-down resistor of nected. Pin A7 is a test pin. 50k. See Applications Information.
PLLIN (Pin A8):
External Clock Synchronization Input to
MARG1 (Pin D12):
This pin is the MSB logic input for the the Phase Detector. This pin is internally terminated to margining function. Together with the MARG0 pin it will SGND with a 50k resistor. Apply a clock with high level determine if margin high, margin low or no margin state above 2V and below INTVCC. See Applications Information. is applied. The pin has an internal pull-down resistor of 50k. See Applications Information.
SGND (Pins H12, H11, G11):
Signal Ground. These pins connect to PGND at output capacitor point. See Figure 17. 4601ahvfc For more information www.linear.com/LTM4601AHV 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Decoupling Requirements Operation Applications Information Typical Applications Package Description Revision History Package Photos Related Parts
