Datasheet ADE9153A (Analog Devices) - 8

ADE9153A Data Sheet ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum
Table 4.
Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these
Parameter Rating
or any other conditions above those indicated in the operational VDD to AGND/DGND −0.3 V to +3.96 V section of this specification is not implied. Operation beyond Analog Input Voltage to AGND/DGND, −0.75 V to +2.2 V IAP, IAN, IBP, IBN, VP, VN1 the maximum operating conditions for extended periods may Reference Input Voltage to AGND/DGND −0.3 V to +2.2 V affect product reliability. Digital Input Voltage to AGND/DGND −0.3 V to +3.96 V
THERMAL RESISTANCE
Digital Output Voltage to AGND/DGND −0.3 V to +3.96 V Thermal performance is directly linked to printed circuit board Operating Temperature (PCB) design and operating environment. Careful attention to Industrial Temperature Range −40°C to +85°C PCB thermal design is required. Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec)2 260°C θJA and θJC are specified for the worst-case conditions, that is, a Electrostatic Discharge (ESD) device soldered in a circuit board for surface-mount packages. Human Body Model (HBM) 4 kV
Table 5. Thermal Resistance
Machine Model (MM) 200 V
Package Type θ 1 2 JA θJC Unit
Field Induced Charged Device Model 1.25 kV CP-32-123 27.83 2.10 °C/W (FICDM) 1 1 The rating of −0.75 V on the analog input pins is limited by protection The θJA measurement uses a 2S2P JEDEC test board. 2 diodes inside the ADE9153A. These pins were tested with 7.5 mA going to The θJC measurement uses a 1S0P JEDEC test board. 3 the pin to simulate a 30× overcurrent condition on the channel, based on All thermal measurements comply with JESD51. the test circuit antialiasing resistor of 150 Ω. 2 Analog Devices, Inc., recommends that reflow profiles used in soldering RoHS-compliant devices conform to J-STD-020D.1 from JEDEC. Refer to
ESD CAUTION
JEDEC for the latest revision of this standard. Rev. 0 | Page 8 of 50 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATIONS CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AUTOCALIBRATION SPI TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE ENERGY ERROR OVER FREQUENCY AND POWER FACTOR RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY SIGNAL-TO-NOISE RATIO (SNR) PERFORMANCE OVER DYNAMIC RANGE TEST CIRCUIT TERMINOLOGY THEORY OF OPERATION mSURE AUTOCALIBRATION FEATURE mSure System Warning Interrupts MEASUREMENTS Current Channel Current Channel Gain, xIGAIN High-Pass Filter Digital Integrator Phase Compensation Voltage Channel RMS and Power Measurements Total RMS Total Active Power Fundamental Reactive Power Total Apparent Power Energy Accumulation, Power Accumulation, and No Load Detection Features Energy Accumulation Energy Accumulation Modes Reset Energy Register on Read Power Accumulation No Load Detection Feature Digital to Frequency Conversion—CFx Output Calibration Frequency (CF) Energy Selection Configuring the CFx Pulse Width CFx Pulse Sign Clearing the CFx Accumulator POWER QUALITY MEASUREMENTS Zero-Crossing Detection CF1/ZX/DREADY Zero-Crossing Timeout Line Period Calculation Angle Measurement One Cycle RMS Measurement Dip and Swell Indication Overcurrent Indication Peak Detection Power Factor Temperature APPLICATIONS INFORMATION INTERRUPTS/EVENTS PIN INTERRUPTS SERVICING INTERRUPTS CF2/ZX/DREADY EVENT PIN ACCESSING ON-CHIP DATA SPI PROTOCOL OVERVIEW UART INTERFACE COMMUNICATION VERIFICATION REGISTERS CRC OF CONFIGURATION REGISTERS CONFIGURATION LOCK REGISTER INFORMATION REGISTER SUMMARY REGISTER DETAILS OUTLINE DIMENSIONS ORDERING GUIDE