Datasheet ADE7854A, ADE7858A, ADE7868A, ADE7878A (Analog Devices) - 10

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ADE7854A/ADE7858A/ADE7868A/ADE7878A Data Sheet TIMING CHARACTERISTICS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C. Note that within the timing tables and diagrams, dual function pin names are referenced by the relevant function only (see the Pin Configuration and Function Descriptions section for ful pin mnemonics and descriptions).
I2C Interface Timing Table 3. Standard Mode Fast Mode Parameter Symbol Min Max Min Max Unit
SCL Clock Frequency fSCL 0 100 0 400 kHz Hold Time for Start and Repeated Start Conditions tHD;STA 4.0 0.6 μs Low Period of SCL Clock tLOW 4.7 1.3 µs High Period of SCL Clock tHIGH 4.0 0.6 µs Setup Time for Repeated Start Condition tSU;STA 4.7 0.6 µs Data Hold Time tHD;DAT 0 3.45 0 0.9 µs Data Setup Time tSU;DAT 250 100 ns Rise Time of SDA and SCL Signals tR 1000 20 300 ns Fall Time of SDA and SCL Signals tF 300 20 300 ns Setup Time for Stop Condition tSU;STO 4.0 0.6 µs Bus Free Time Between a Stop and Start Condition tBUF 4.7 1.3 µs Pulse Width of Suppressed Spikes tSP N/A1 50 ns 1 N/A means not applicable.
SDA tBUF t t t F SU;DAT tHD;STA tSP R tR tF tLOW SCL tHD;STAt t HD;DAT t SU;STO t SU;STA HIGH
005
START REPEATED START STOP START CONDITION CONDITION CONDITION CONDITION
136- 11 Figure 5. I2C Interface Timing Rev. C | Page 10 of 96 Document Outline FEATURES GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAMS SPECIFICATIONS TIMING CHARACTERISTICS I2C Interface Timing SPI Interface Timing HSDC Interface Timing Load Circuit for Timing Specifications ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT TERMINOLOGY POWER MANAGEMENT PSM0 NORMAL POWER MODE (ALL DEVICES) PSM1 REDUCED POWER MODE (ADE7868A AND ADE7878A ONLY) PSM2 LOW POWER MODE (ADE7868A AND ADE7878A ONLY) PSM2 Interrupt Mode (Default) Setting the Measurement Period Setting the Threshold PSM2 IRQ1/ Only Mode PSM3 SLEEP MODE (ALL DEVICES) POWER-UP PROCEDURE HARDWARE RESET SOFTWARE RESET THEORY OF OPERATION ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialiasing Filter ADC Transfer Function CURRENT CHANNEL ADC Current Waveform Gain Registers Current Channel High-Pass Filter Current Channel Sampling di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR VOLTAGE CHANNEL ADC Voltage Waveform Gain Registers Voltage Channel HPF Voltage Channel Sampling CHANGING THE PHASE VOLTAGE DATAPATH POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Phase Sequence Detection Time Interval Between Phases Delays Between Voltages and Currents Delays Between Phase Voltages Delays Between Phase Currents Power Factor Period Measurement Phase Voltage Sag Detection Sag Level Set Peak Detection Overvoltage and Overcurrent Detection Overvoltage and Overcurrent Level Set Neutral Current Mismatch—ADE7868A and ADE7878A PHASE COMPENSATION REFERENCE CIRCUIT DIGITAL SIGNAL PROCESSOR ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Low Ripple Current RMS Current RMS Offset Compensation Current Mean Absolute Value Calculation—ADE7868A and ADE7878A Only Current MAV Gain and Offset Compensation Voltage RMS Calculation Low Ripple Voltage RMS Voltage RMS Offset Compensation Voltage RMS in 3-Phase, 3-Wire Delta Configurations ACTIVE POWER CALCULATION Total Active Power Calculation Fundamental Active Power Calculation—ADE7878A Only Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation Active Energy Calculation Integration Time Under Steady Load Energy Accumulation Modes Line Cycle Active Energy Accumulation Mode REACTIVE POWER CALCULATION—ADE7858A, ADE7868A, ADE7878A ONLY Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Energy Calculation Integration Time Under Steady Load Energy Accumulation Modes Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Power Calculation Using VNOM Apparent Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Line Cycle Apparent Energy Accumulation Mode WAVEFORM SAMPLING MODE ENERGY TO FREQUENCY CONVERSION Synchronizing Energy Registers with the CFx Outputs CFx Outputs for Various Accumulation Modes Sign of Sum-of-Phase Powers in the CFx Datapath NO LOAD CONDITION No Load Detection Based on Total Active and Reactive Powers No Load Detection Based on Fundamental Active and Reactive Powers—ADE7878A Only No Load Detection Based on Apparent Power CHECKSUM REGISTER INTERRUPTS Using the Interrupts with an MCU APPLICATIONS INFORMATION QUICK SETUP OF DEVICES AS ENERGY METERS CRYSTAL CIRCUIT LAYOUT GUIDELINES ADE7878A EVALUATION BOARD DIE VERSION SILICON ANOMALY ADE7854A/ADE7858A/ADE7868A/ADE7878A FUNCTIONALITY ISSUES FUNCTIONALITY ISSUES SERIAL INTERFACES SERIAL INTERFACE SELECTION COMMUNICATION VERIFICATION I2C-COMPATIBLE INTERFACE I2C Write Operation I2C Read Operation SPI-COMPATIBLE INTERFACE SPI Write Operation SPI Read Operation SPI Burst Read Operation HSDC INTERFACE REGISTER LIST OUTLINE DIMENSIONS ORDERING GUIDE