Datasheet ADE7953 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Single Phase Multifunction Metering IC with Neutral Current Measurement |
| Pages / Page | 72 / 9 — Data Sheet. ADE7953. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. /Tx. … |
| Revision | C |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
Data Sheet. ADE7953. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. /Tx. L/R. I/S. O/S. IRQ. ZX 1. 21 ZX_I. RESET 2. 20 REVP. VINTD 3. 19 CLKOUT
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Data Sheet ADE7953 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS x /Tx L/R A C D I/S K O/S 2 1 OS IS CL CS M M S CF CF IRQ 28 27 26 25 24 23 22 ZX 1 21 ZX_I RESET 2 20 REVP VINTD 3 19 CLKOUT ADE7953 DGND 4 18 CLKIN TOP VIEW IAP 5 17 VDD (Not to Scale) IAN 6 16 AGND PULL_HIGH 7 15 VINTA 8 9 1 10 1 12 13 14 F IGH IBP IBN VN VP RE H LOW LL_ LL_ U U P P NOTES 1. CREATE A SIMILAR PAD ON THE PCB UNDER THE EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE PAD ON THE PCB
004
TO CONFER MECHANICAL STRENGTH TO THE PACKAGE. CONNECT THE PAD TO AGND AND DGND.
09320- Figure 4. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 ZX Voltage Channel Zero-Crossing Output Pin. See the Voltage Channel Zero Crossing section. This pin can be configured to output a range of alternative power quality signals (see the Alternative Output Functions section). 2 RESET Active Low Reset Input. To initiate a hardware reset, this pin must be brought low for at minimum of 10 µs. 3 VINTD This pin provides access to the 2.5 V digital LDO. This pin should be decoupled with a 4.7 µF capacitor in parallel with a 100 nF ceramic capacitor. 4 DGND Ground Reference for the Digital Circuitry. 5, 6 IAP, IAN Analog Input for Current Channel A (Phase Current Channel). This differential voltage input has a maximum input range of ±500 mV. The maximum pin voltage for single-ended use is ±250 mV. The PGA associated with this input has a maximum gain stage of 22 (see the Analog Inputs section). 7, 8 PULL_HIGH These pins should be connected to VDD for proper operation. 9, 10 IBP, IBN Analog Input for Current Channel B (Neutral Current Channel). This differential voltage input has a maximum input range of ±500 mV. The PGA associated with this input has a maximum gain of 16 (see the Analog Inputs section). 11, 12 VN, VP Analog Input for Voltage Channel. This differential voltage input has a maximum input range of ±500 mV. The PGA associated with this input has a maximum gain of 16 (see the Analog Inputs section). 13 REF This pin provides access to the on-chip voltage reference. The internal reference has a nominal voltage of 1.2 V. This pin should be decoupled with a 4.7 µF capacitor in parallel with a 100 nF ceramic capacitor. Alternatively, an external reference voltage of 1.2 V can be applied to this pin (see the Reference Circuit section). 14 PULL_LOW This pin should be connected to AGND for proper operation. 15 VINTA This pin provides access to the 2.5 V analog LDO. This pin should be decoupled with a 4.7 µF capacitor in parallel with a 100 nF ceramic capacitor. 16 AGND Ground Reference for the Analog Circuitry. 17 VDD Power Supply (3.3 V) for the ADE7953. For specified operation, the input to this pin should be within 3.3 V ± 10%. This pin should be decoupled with a 10 µF capacitor in parallel with a 100 nF ceramic capacitor. 18 CLKIN Master Clock Input for the ADE7953. An external clock can be provided at this input. Alternatively, a parallel resonant AT crystal can be connected across the CLKIN and CLKOUT pins to provide a clock source for the ADE7953. The clock frequency for specified operation is 3.58 MHz. Ceramic load capacitors of a few tens of picofarads should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for the load capacitance requirements. 19 CLKOUT A crystal can be connected across this pin and CLKIN to provide a clock source for the ADE7953. Rev. C | Page 9 of 72 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS SPI Interface Timing SPI Interface Timing Diagram I2C Interface Timing I2C Interface Timing Diagram ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT TERMINOLOGY ADE7953 POWER-UP PROCEDURE REQUIRED REGISTER SETTING THEORY OF OPERATION ANALOG INPUTS Current Channel A Current Channel B Voltage Channel ANALOG-TO-DIGITAL CONVERSION Oversampling Noise Shaping Antialiasing Filter CURRENT CHANNEL ADCS di/dt Current Sensor and Digital Integrator VOLTAGE CHANNEL ADC REFERENCE CIRCUIT ROOT MEAN SQUARE MEASUREMENT CURRENT CHANNEL RMS CALCULATION VOLTAGE CHANNEL RMS CALCULATION ACTIVE POWER CALCULATION SIGN OF ACTIVE POWER CALCULATION ACTIVE ENERGY CALCULATION Active Energy Integration Time Under Steady Load Active Energy Line Cycle Accumulation Mode ACTIVE ENERGY ACCUMULATION MODES Signed Accumulation Mode Positive-Only Accumulation Mode Absolute Accumulation Mode REACTIVE POWER CALCULATION SIGN OF REACTIVE POWER CALCULATION REACTIVE ENERGY CALCULATION Reactive Energy Integration Time Under Steady Load Reactive Energy Line Cycle Accumulation Mode REACTIVE ENERGY ACCUMULATION MODES Signed Accumulation Mode Antitamper Accumulation Mode Absolute Accumulation Mode APPARENT POWER CALCULATION APPARENT ENERGY CALCULATION Apparent Energy Integration Time Under Steady Load Apparent Energy Line Cycle Accumulation Mode AMPERE-HOUR ACCUMULATION ENERGY-TO-FREQUENCY CONVERSION PULSE OUTPUT CHARACTERISTICS ENERGY CALIBRATION GAIN CALIBRATION Current Channel Gain Adjustment PHASE CALIBRATION OFFSET CALIBRATION Power Offsets RMS Offsets PERIOD MEASUREMENT INSTANTANEOUS POWERS AND WAVEFORM SAMPLING POWER FACTOR USING THE LINE CYCLE ACCUMULATION MODE TO DETERMINE THE POWER FACTOR POWER FACTOR WITH NO-LOAD DETECTION ANGLE MEASUREMENT NO-LOAD DETECTION SETTING THE NO-LOAD THRESHOLDS ACTIVE ENERGY NO-LOAD DETECTION Active Energy No-Load Interrupt Active Energy No-Load Status Bits REACTIVE ENERGY NO-LOAD DETECTION Reactive Energy No-Load Interrupt Reactive Energy No-Load Status Bits APPARENT ENERGY NO-LOAD DETECTION Apparent Energy No-Load Interrupt Apparent Energy No-Load Status Bits ZERO-CROSSING DETECTION ZERO-CROSSING OUTPUT PINS Voltage Channel Zero Crossing Current Channel Zero Crossing ZERO-CROSSING INTERRUPTS ZERO-CROSSING TIMEOUT ZERO-CROSSING THRESHOLD VOLTAGE SAG DETECTION SETTING THE SAGCYC REGISTER SETTING THE SAGLVL REGISTER VOLTAGE SAG INTERRUPT PEAK DETECTION INDICATION OF POWER DIRECTION REVERSE POWER SIGN INDICATION OVERCURRENT AND OVERVOLTAGE DETECTION SETTING THE OVLVL AND OILVL REGISTERS OVERVOLTAGE AND OVERCURRENT INTERRUPTS ALTERNATIVE OUTPUT FUNCTIONS ADE7953 INTERRUPTS PRIMARY INTERRUPTS (VOLTAGE CHANNEL AND CURRENT CHANNEL A) CURRENT CHANNEL B INTERRUPTS COMMUNICATING WITH THE ADE7953 COMMUNICATION AUTODETECTION LOCKING THE COMMUNICATION INTERFACE SPI INTERFACE I2C INTERFACE I2C Write Operations I2C Read Operations UART INTERFACE UART Read UART Write COMMUNICATION VERIFICATION AND SECURITY WRITE PROTECTION COMMUNICATION VERIFICATION CHECKSUM REGISTER ADE7953 REGISTERS ADE7953 REGISTER DESCRIPTIONS Interrupt Enable and Interrupt Status Registers Current Channel A and Voltage Channel Registers Current Channel B Registers LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADE7953 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS x /Tx L/R A C D I/S K O/S 2 1 OS IS CL CS M M S CF CF IRQ 28 27 26 25 24 23 22 ZX 1 21 ZX_I RESET 2 20 REVP VINTD 3 19 CLKOUT ADE7953 DGND 4 18 CLKIN TOP VIEW IAP 5 17 VDD (Not to Scale) IAN 6 16 AGND PULL_HIGH 7 15 VINTA 8 9 1 10 1 12 13 14 F IGH IBP IBN VN VP RE H LOW LL_ LL_ U U P P NOTES 1. CREATE A SIMILAR PAD ON THE PCB UNDER THE EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE PAD ON THE PCB
004
TO CONFER MECHANICAL STRENGTH TO THE PACKAGE. CONNECT THE PAD TO AGND AND DGND.
09320- Figure 4. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 ZX Voltage Channel Zero-Crossing Output Pin. See the Voltage Channel Zero Crossing section. This pin can be configured to output a range of alternative power quality signals (see the Alternative Output Functions section). 2 RESET Active Low Reset Input. To initiate a hardware reset, this pin must be brought low for at minimum of 10 µs. 3 VINTD This pin provides access to the 2.5 V digital LDO. This pin should be decoupled with a 4.7 µF capacitor in parallel with a 100 nF ceramic capacitor. 4 DGND Ground Reference for the Digital Circuitry. 5, 6 IAP, IAN Analog Input for Current Channel A (Phase Current Channel). This differential voltage input has a maximum input range of ±500 mV. The maximum pin voltage for single-ended use is ±250 mV. The PGA associated with this input has a maximum gain stage of 22 (see the Analog Inputs section). 7, 8 PULL_HIGH These pins should be connected to VDD for proper operation. 9, 10 IBP, IBN Analog Input for Current Channel B (Neutral Current Channel). This differential voltage input has a maximum input range of ±500 mV. The PGA associated with this input has a maximum gain of 16 (see the Analog Inputs section). 11, 12 VN, VP Analog Input for Voltage Channel. This differential voltage input has a maximum input range of ±500 mV. The PGA associated with this input has a maximum gain of 16 (see the Analog Inputs section). 13 REF This pin provides access to the on-chip voltage reference. The internal reference has a nominal voltage of 1.2 V. This pin should be decoupled with a 4.7 µF capacitor in parallel with a 100 nF ceramic capacitor. Alternatively, an external reference voltage of 1.2 V can be applied to this pin (see the Reference Circuit section). 14 PULL_LOW This pin should be connected to AGND for proper operation. 15 VINTA This pin provides access to the 2.5 V analog LDO. This pin should be decoupled with a 4.7 µF capacitor in parallel with a 100 nF ceramic capacitor. 16 AGND Ground Reference for the Analog Circuitry. 17 VDD Power Supply (3.3 V) for the ADE7953. For specified operation, the input to this pin should be within 3.3 V ± 10%. This pin should be decoupled with a 10 µF capacitor in parallel with a 100 nF ceramic capacitor. 18 CLKIN Master Clock Input for the ADE7953. An external clock can be provided at this input. Alternatively, a parallel resonant AT crystal can be connected across the CLKIN and CLKOUT pins to provide a clock source for the ADE7953. The clock frequency for specified operation is 3.58 MHz. Ceramic load capacitors of a few tens of picofarads should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for the load capacitance requirements. 19 CLKOUT A crystal can be connected across this pin and CLKIN to provide a clock source for the ADE7953. Rev. C | Page 9 of 72 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS SPI Interface Timing SPI Interface Timing Diagram I2C Interface Timing I2C Interface Timing Diagram ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT TERMINOLOGY ADE7953 POWER-UP PROCEDURE REQUIRED REGISTER SETTING THEORY OF OPERATION ANALOG INPUTS Current Channel A Current Channel B Voltage Channel ANALOG-TO-DIGITAL CONVERSION Oversampling Noise Shaping Antialiasing Filter CURRENT CHANNEL ADCS di/dt Current Sensor and Digital Integrator VOLTAGE CHANNEL ADC REFERENCE CIRCUIT ROOT MEAN SQUARE MEASUREMENT CURRENT CHANNEL RMS CALCULATION VOLTAGE CHANNEL RMS CALCULATION ACTIVE POWER CALCULATION SIGN OF ACTIVE POWER CALCULATION ACTIVE ENERGY CALCULATION Active Energy Integration Time Under Steady Load Active Energy Line Cycle Accumulation Mode ACTIVE ENERGY ACCUMULATION MODES Signed Accumulation Mode Positive-Only Accumulation Mode Absolute Accumulation Mode REACTIVE POWER CALCULATION SIGN OF REACTIVE POWER CALCULATION REACTIVE ENERGY CALCULATION Reactive Energy Integration Time Under Steady Load Reactive Energy Line Cycle Accumulation Mode REACTIVE ENERGY ACCUMULATION MODES Signed Accumulation Mode Antitamper Accumulation Mode Absolute Accumulation Mode APPARENT POWER CALCULATION APPARENT ENERGY CALCULATION Apparent Energy Integration Time Under Steady Load Apparent Energy Line Cycle Accumulation Mode AMPERE-HOUR ACCUMULATION ENERGY-TO-FREQUENCY CONVERSION PULSE OUTPUT CHARACTERISTICS ENERGY CALIBRATION GAIN CALIBRATION Current Channel Gain Adjustment PHASE CALIBRATION OFFSET CALIBRATION Power Offsets RMS Offsets PERIOD MEASUREMENT INSTANTANEOUS POWERS AND WAVEFORM SAMPLING POWER FACTOR USING THE LINE CYCLE ACCUMULATION MODE TO DETERMINE THE POWER FACTOR POWER FACTOR WITH NO-LOAD DETECTION ANGLE MEASUREMENT NO-LOAD DETECTION SETTING THE NO-LOAD THRESHOLDS ACTIVE ENERGY NO-LOAD DETECTION Active Energy No-Load Interrupt Active Energy No-Load Status Bits REACTIVE ENERGY NO-LOAD DETECTION Reactive Energy No-Load Interrupt Reactive Energy No-Load Status Bits APPARENT ENERGY NO-LOAD DETECTION Apparent Energy No-Load Interrupt Apparent Energy No-Load Status Bits ZERO-CROSSING DETECTION ZERO-CROSSING OUTPUT PINS Voltage Channel Zero Crossing Current Channel Zero Crossing ZERO-CROSSING INTERRUPTS ZERO-CROSSING TIMEOUT ZERO-CROSSING THRESHOLD VOLTAGE SAG DETECTION SETTING THE SAGCYC REGISTER SETTING THE SAGLVL REGISTER VOLTAGE SAG INTERRUPT PEAK DETECTION INDICATION OF POWER DIRECTION REVERSE POWER SIGN INDICATION OVERCURRENT AND OVERVOLTAGE DETECTION SETTING THE OVLVL AND OILVL REGISTERS OVERVOLTAGE AND OVERCURRENT INTERRUPTS ALTERNATIVE OUTPUT FUNCTIONS ADE7953 INTERRUPTS PRIMARY INTERRUPTS (VOLTAGE CHANNEL AND CURRENT CHANNEL A) CURRENT CHANNEL B INTERRUPTS COMMUNICATING WITH THE ADE7953 COMMUNICATION AUTODETECTION LOCKING THE COMMUNICATION INTERFACE SPI INTERFACE I2C INTERFACE I2C Write Operations I2C Read Operations UART INTERFACE UART Read UART Write COMMUNICATION VERIFICATION AND SECURITY WRITE PROTECTION COMMUNICATION VERIFICATION CHECKSUM REGISTER ADE7953 REGISTERS ADE7953 REGISTER DESCRIPTIONS Interrupt Enable and Interrupt Status Registers Current Channel A and Voltage Channel Registers Current Channel B Registers LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE
