Datasheet ADE7759 (Analog Devices) - 7

ADE7759 PIN CONFIGURATION RESET 1 20 DIN DVDD 2 19 DOUT AVDD 3 18 SCLK V1P 4 17 CS V1N 5 ADE7759 16 CLKOUT TOP VIEW V2N 6 15 CLKIN (Not to Scale) V2P 7 14 IRQ AGND 8 13 SAG REFIN/OUT 9 12 ZX DGND 10 11 CF PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description
1 RESET Reset Pin for the ADE7759. A logic low on this pin will hold the ADCs and digital circuitry (including the serial interface) in a reset condition. 2 DVDD Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7759. The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 mF capacitor in parallel with a ceramic 100 nF capacitor. 3 AVDD Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7759. The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling method. This pin should be decoupled to AGND with a 10 mF capacitor in parallel with a ceramic 100 nF capacitor. 4, 5 V1P, V1N Analog Inputs for Channel 1. This channel is intended for use with the di/dt current transducers such as Rogowski coil, or other current sensors such as shunt or current transformer (CT). These inputs are fully differential voltage inputs with maximum differential input signal levels of ±0.5 V, ±0.25 V, and ± 0.125 V, depending on the full-scale selection—see Analog Inputs section. Channel 1 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ± 0.5 V. Both inputs have internal ESD protection circuitry. In addi- tion, an overvoltage of ± 6 V can be sustained on these inputs without risk of permanent damage. 6, 7 V2N, V2P Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These inputs are fully differential voltage inputs with a maximum differential signal level of ± 0.5 V. Channel 2 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ± 0.5 V. Both inputs have internal ESD protection circuitry, and an over- voltage of ±6 V can be sustained on these inputs without risk of permanent damage. 8 AGND This pin provides the ground reference for the analog circuitry in the ADE7759, i.e., ADCs and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, e.g., antialiasing filters, current and voltage transducers. To keep ground noise around the ADE7759 to a minimum, the quiet ground plane should be connected to the digital ground plane at only one point. It is acceptable to place the entire device on the analog ground plane—see Application Information section. 9 REFIN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.4 V ± 8% and a typical temperature coefficient of 20 ppm/∞C. An external reference source may be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 mF capacitor in parallel with a 100 nF capacitor. 10 DGND This provides the ground reference for the digital circuitry in the ADE7759, i.e., multiplier, filters, and frequency output (CF). Because the digital return currents in the ADE7759 are small, it is acceptable to connect this pin to the analog ground plane of the system—see Application Information section. However, high bus capacitance on the DOUT pin may result in noisy digital current that affects performance. 11 CF Calibration Frequency Logic Output. The CF logic output gives Active Power information. This output is intended to be used for operational and calibration purposes. The full-scale output fre- quency can be adjusted by writing to the APGAIN, CFNUM, and CFDEN registers—see Energy to Frequency Conversion section. REV. A –7– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY MEASUREMENT ERROR PHASE ERROR BETWEEN CHANNELS POWER SUPPLY REJECTION ADC OFFSET ERROR GAIN ERROR GAIN ERROR MATCH Typical Performance Characteristics Test Circuits ANALOG INPUTS di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR ZERO CROSSING DETECTION LINE VOLTAGE SAG DETECTION Sag Level Set POWER SUPPLY MONITOR INTERRUPTS Using the ADE7759 Interrupts with an MCU Interrupt Timing TEMPERATURE MEASUREMENT ANALOG-TO-DIGITAL CONVERSION Antialias Filter ADC Transfer Function Reference Circuit CHANNEL 1 ADC Channel 1 ADC Gain Adjust Channel 1 Sampling CHANNEL 1 AND CHANNEL 2 WAVEFORM SAMPLING MODE CHANNEL 2 ADC Channel 2 Sampling PHASE COMPENSATION ACTIVE POWER CALCULATION ENERGY CALCULATION Integration Time under Steady Load POWER OFFSET CALIBRATION ENERGY-TO-FREQUENCY CONVERSION LINE CYCLE ENERGY ACCUMULATION MODE CALIBRATING THE ENERGY METER Calculating the Average Active Power Calibrating the Frequency at CF Energy Meter Display CLKIN FREQUENCY SUSPENDING THE ADE7759 FUNCTIONALITY APPLICATION INFORMATION SERIAL INTERFACE Serial Write Operation Serial Read Operation CHECKSUM REGISTER REGISTER DESCRIPTIONS Communications Register Mode Register (06H) Interrupt Status Register (04H) Reset Interrupt Status Register (05H) CH1OS Register (08H) OUTLINE DIMENSIONS Revision History