Datasheet RH1056A (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | Precision, High Speed, JFET Input Operational Amplifier |
| Pages / Page | 4 / 3 — TABLE 1A: ELECTRICAL CHARACTERISTICS Note 1:. Note 3:. Note 4:. Note 2:. … |
| Revision | D |
| File Format / Size | PDF / 190 Kb |
| Document Language | English |
TABLE 1A: ELECTRICAL CHARACTERISTICS Note 1:. Note 3:. Note 4:. Note 2:. Note 5:
Model Line for this Datasheet
Text Version of Document
RH1056A
TABLE 1A: ELECTRICAL CHARACTERISTICS Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 3:
Unless otherwise stated, VS = ±15V; and VOS, IB and IOS are may cause permanent damage to the device. Exposure to any Absolute measured at VCM = 0V. Maximum Rating condition for extended periods may affect device
Note 4:
The input bias currents are junction leakage currents which reliability and lifetime. approximately double for every 10°C increase in the junction temperature,
Note 2:
Unless otherwise specified, the absolute maximum negative input TJ. Due to limited production test time, the input bias currents measured voltage is equal to the negative power supply voltage. Offset voltage is are correlated to junction temperature. In normal operation the junction measured under two different conditions: (a) approximately 0.5 seconds temperature rises above the ambient temperature as a result of internal after application of power, (b) at TA = 25°C only, with the chip heated to power dissipation, PD. TJ = TA + (θJA • PD) where θJA is the thermal approximately 45°C to account for chip temperature rise when the device resistance from junction to ambient. is fully warmed up.
Note 5:
Unless otherwise stated, VS = ±15V, VCM = 0V and TA = 25°C.
TABLE 2: ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUP PDA Test Notes
Final Electrical Test Requirements (Method 5004) 1*,2,3,4,5,6, 7 The PDA is specified as 5% based on failures from group A, subgroup 1, tests after cooldown as the final electrical test in accordance with method Group A Test Requirements (Method 5005) 1,2,3,4,5,6, 7 5004 of MIL-STD-883. The verified failures of group A, subgroup 1, after Group B and D for Class S, and 1 burn-in divided by the total number of devices submitted for burn-in in Class C and D for Class B** that lot shall be used to determine the percent for the lot. End Point Electrical Parameters (Method 5005) Linear Technology Corporation reserves the right to test to tighter limits *PDA applies to subgroup 1. See PDA Test Notes. than those given. **For D3, D4, B5 and B6 VOS Limit as follows W Package H Package 500µV 700µV
TOTAL DOSE BIAS CIRCUIT
10k 15V 0.1µF 2 – 7 6 10k 3 + 8V 4 0.1µF RH1056A BC –15V
REVISION HISTORY (Revision history begins at Rev D) REV DATE DESCRIPTION PAGE NUMBER
D 06/18 Corrected parametric units for input noise voltage density All Pages Rev D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications For more information www.a subject to change without notice. No license is granted by implication or other nalog.com wise under any patent or patent rights of Analog Devices. 3 Document Outline Package Information Burn-In Circuit Table 2: Electrical Test Requirements Total Dose Bias Circuit Revision History
TABLE 1A: ELECTRICAL CHARACTERISTICS Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 3:
Unless otherwise stated, VS = ±15V; and VOS, IB and IOS are may cause permanent damage to the device. Exposure to any Absolute measured at VCM = 0V. Maximum Rating condition for extended periods may affect device
Note 4:
The input bias currents are junction leakage currents which reliability and lifetime. approximately double for every 10°C increase in the junction temperature,
Note 2:
Unless otherwise specified, the absolute maximum negative input TJ. Due to limited production test time, the input bias currents measured voltage is equal to the negative power supply voltage. Offset voltage is are correlated to junction temperature. In normal operation the junction measured under two different conditions: (a) approximately 0.5 seconds temperature rises above the ambient temperature as a result of internal after application of power, (b) at TA = 25°C only, with the chip heated to power dissipation, PD. TJ = TA + (θJA • PD) where θJA is the thermal approximately 45°C to account for chip temperature rise when the device resistance from junction to ambient. is fully warmed up.
Note 5:
Unless otherwise stated, VS = ±15V, VCM = 0V and TA = 25°C.
TABLE 2: ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUP PDA Test Notes
Final Electrical Test Requirements (Method 5004) 1*,2,3,4,5,6, 7 The PDA is specified as 5% based on failures from group A, subgroup 1, tests after cooldown as the final electrical test in accordance with method Group A Test Requirements (Method 5005) 1,2,3,4,5,6, 7 5004 of MIL-STD-883. The verified failures of group A, subgroup 1, after Group B and D for Class S, and 1 burn-in divided by the total number of devices submitted for burn-in in Class C and D for Class B** that lot shall be used to determine the percent for the lot. End Point Electrical Parameters (Method 5005) Linear Technology Corporation reserves the right to test to tighter limits *PDA applies to subgroup 1. See PDA Test Notes. than those given. **For D3, D4, B5 and B6 VOS Limit as follows W Package H Package 500µV 700µV
TOTAL DOSE BIAS CIRCUIT
10k 15V 0.1µF 2 – 7 6 10k 3 + 8V 4 0.1µF RH1056A BC –15V
REVISION HISTORY (Revision history begins at Rev D) REV DATE DESCRIPTION PAGE NUMBER
D 06/18 Corrected parametric units for input noise voltage density All Pages Rev D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications For more information www.a subject to change without notice. No license is granted by implication or other nalog.com wise under any patent or patent rights of Analog Devices. 3 Document Outline Package Information Burn-In Circuit Table 2: Electrical Test Requirements Total Dose Bias Circuit Revision History
