Datasheet LT3430, LT3430-1 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | High Voltage, 3A, 200kHz/100kHz Step-Down Switching Regulators |
| Pages / Page | 28 / 6 — PIN FUNCTIONS. GND (Pins 1, 8, 9, 16, 17):. C (Pin 11):. FB (Pin 12):. SW … |
| File Format / Size | PDF / 335 Kb |
| Document Language | English |
PIN FUNCTIONS. GND (Pins 1, 8, 9, 16, 17):. C (Pin 11):. FB (Pin 12):. SW (Pins 2, 5):. VIN (Pins 3, 4):. SYNC (Pin 14):. N (Pin 15):
Model Line for this Datasheet
Text Version of Document
LT3430/LT3430-1
PIN FUNCTIONS GND (Pins 1, 8, 9, 16, 17):
The GND pin connections act This architecture increases effi ciency especially when the as the reference for the regulated output, so load regulation input voltage is much higher than the output. Minimum will suffer if the “ground” end of the load is not at the same output voltage setting for this mode of operation is 3V. voltage as the GND pins of the IC. This condition will occur
V
when load current or other currents fl ow through metal
C (Pin 11):
The VC pin is the output of the error amplifi er and the input of the peak switch current comparator. It is paths between the GND pins and the load ground. Keep the normally used for frequency compensation, but can also paths between the GND pins and the load ground short and serve as a current clamp or control loop override. V use a ground plane when possible. The FE package has an C sits at about 0.9V for light loads and 2.1V at maximum load. exposed pad that is fused to the GND pins. The pad (Pin It can be driven to ground to shut off the regulator, but if 17) should be soldered to the copper ground plane under driven high, current must be limited to 4mA. the device to reduce thermal resistance. (See Applications Information—Layout Considerations.)
FB (Pin 12):
The feedback pin is used to set the output voltage using an external voltage divider that generates
SW (Pins 2, 5):
The switch pin is the emitter of the on-chip 1.22V at the pin for the desired output voltage. Three power NPN switch. This pin is driven up to the input pin additional functions are performed by the FB pin. When voltage during switch on time. Inductor current drives the the pin voltage drops below 0.6V, switch current limit is switch pin voltage negative during switch off time. Negative reduced and the external SYNC function is disabled. Below voltage is clamped with the external catch diode. Maximum 0.8V, switching frequency is also reduced. See Feedback negative switch voltage allowed is –0.8V. Pin Functions in Applications Information for details.
VIN (Pins 3, 4):
This is the collector of the on-chip power
SYNC (Pin 14):
The SYNC pin is used to synchronize the NPN switch. VIN powers the internal control circuitry when internal oscillator to an external signal. It is directly logic a voltage on the BIAS pin is not present. High dI/dt edges compatible and can be driven with any signal between 10% occur on this pin during switch turn on and off. Keep the and 90% duty cycle. The synchronizing range is 125kHz path short from the VIN pin through the input bypass to 250kHz for the LT3430-1 and 228kHz to 700kHz for the capacitor, through the catch diode back to SW. All trace LT3430. See Synchronizing in Applications Information inductance in this path creates voltage spikes at switch for details. off, adding to the VCE voltage across the internal NPN. ⎯
S
⎯
H
⎯
D
⎯
N (Pin 15):
The ⎯S⎯H⎯D⎯N pin is used to turn off the
BOOST (Pin 6):
The BOOST pin is used to provide a drive regulator and to reduce input drain current to a few mi- voltage, higher than the input voltage, to the internal bipolar croamperes. This pin has two thresholds: one at 2.38V to NPN power switch. Without this added voltage, the typical disable switching and a second at 0.4V to force complete switch voltage loss would be about 1.5V. The additional micropower shutdown. The 2.38V threshold functions BOOST voltage allows the switch to saturate and voltage as an accurate undervoltage lockout (UVLO); sometimes loss approximates that of a 0.1Ω FET structure. used to prevent the regulator from delivering power until
NC (Pins 7, 13):
No Connection. the input voltage has reached a predetermined level.
BIAS (Pin 10):
The BIAS pin is used to improve effi ciency If the ⎯S⎯H⎯D⎯N pin functions are not required, the pin can when operating at higher input voltages and light load cur- either be left open (to allow an internal bias current to lift rent. Connecting this pin to the regulated output voltage the pin to a default high state) or be forced high to a level forces most of the internal circuitry to draw its operating not to exceed 6V. current from the output voltage rather than the input supply. 34301fa 6
PIN FUNCTIONS GND (Pins 1, 8, 9, 16, 17):
The GND pin connections act This architecture increases effi ciency especially when the as the reference for the regulated output, so load regulation input voltage is much higher than the output. Minimum will suffer if the “ground” end of the load is not at the same output voltage setting for this mode of operation is 3V. voltage as the GND pins of the IC. This condition will occur
V
when load current or other currents fl ow through metal
C (Pin 11):
The VC pin is the output of the error amplifi er and the input of the peak switch current comparator. It is paths between the GND pins and the load ground. Keep the normally used for frequency compensation, but can also paths between the GND pins and the load ground short and serve as a current clamp or control loop override. V use a ground plane when possible. The FE package has an C sits at about 0.9V for light loads and 2.1V at maximum load. exposed pad that is fused to the GND pins. The pad (Pin It can be driven to ground to shut off the regulator, but if 17) should be soldered to the copper ground plane under driven high, current must be limited to 4mA. the device to reduce thermal resistance. (See Applications Information—Layout Considerations.)
FB (Pin 12):
The feedback pin is used to set the output voltage using an external voltage divider that generates
SW (Pins 2, 5):
The switch pin is the emitter of the on-chip 1.22V at the pin for the desired output voltage. Three power NPN switch. This pin is driven up to the input pin additional functions are performed by the FB pin. When voltage during switch on time. Inductor current drives the the pin voltage drops below 0.6V, switch current limit is switch pin voltage negative during switch off time. Negative reduced and the external SYNC function is disabled. Below voltage is clamped with the external catch diode. Maximum 0.8V, switching frequency is also reduced. See Feedback negative switch voltage allowed is –0.8V. Pin Functions in Applications Information for details.
VIN (Pins 3, 4):
This is the collector of the on-chip power
SYNC (Pin 14):
The SYNC pin is used to synchronize the NPN switch. VIN powers the internal control circuitry when internal oscillator to an external signal. It is directly logic a voltage on the BIAS pin is not present. High dI/dt edges compatible and can be driven with any signal between 10% occur on this pin during switch turn on and off. Keep the and 90% duty cycle. The synchronizing range is 125kHz path short from the VIN pin through the input bypass to 250kHz for the LT3430-1 and 228kHz to 700kHz for the capacitor, through the catch diode back to SW. All trace LT3430. See Synchronizing in Applications Information inductance in this path creates voltage spikes at switch for details. off, adding to the VCE voltage across the internal NPN. ⎯
S
⎯
H
⎯
D
⎯
N (Pin 15):
The ⎯S⎯H⎯D⎯N pin is used to turn off the
BOOST (Pin 6):
The BOOST pin is used to provide a drive regulator and to reduce input drain current to a few mi- voltage, higher than the input voltage, to the internal bipolar croamperes. This pin has two thresholds: one at 2.38V to NPN power switch. Without this added voltage, the typical disable switching and a second at 0.4V to force complete switch voltage loss would be about 1.5V. The additional micropower shutdown. The 2.38V threshold functions BOOST voltage allows the switch to saturate and voltage as an accurate undervoltage lockout (UVLO); sometimes loss approximates that of a 0.1Ω FET structure. used to prevent the regulator from delivering power until
NC (Pins 7, 13):
No Connection. the input voltage has reached a predetermined level.
BIAS (Pin 10):
The BIAS pin is used to improve effi ciency If the ⎯S⎯H⎯D⎯N pin functions are not required, the pin can when operating at higher input voltages and light load cur- either be left open (to allow an internal bias current to lift rent. Connecting this pin to the regulated output voltage the pin to a default high state) or be forced high to a level forces most of the internal circuitry to draw its operating not to exceed 6V. current from the output voltage rather than the input supply. 34301fa 6
