Datasheet AD8366 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | DC to 600 MHz, Dual-Digital Variable Gain Amplifiers |
| Pages / Page | 28 / 7 — Data Sheet. AD8366. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. PPA. … |
| Revision | B |
| File Format / Size | PDF / 893 Kb |
| Document Language | English |
Data Sheet. AD8366. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. PPA. PMA. OFS. CCM. VPSO. SEN. VPSIA 1. 24 BIT0/CS. IPPA 2. 23 BIT1/SDAT. IPMA 3
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Data Sheet AD8366 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A A A B CA MA PPA PMA DE OFS CCM VC VPSO O O SEN 32 31 30 29 28 27 26 25 VPSIA 1 24 BIT0/CS IPPA 2 23 BIT1/SDAT IPMA 3 22 BIT2/SCLK AD8366 ENBL 4 21 BIT3 ICOM 5 TOP VIEW 20 OCOM (Not to Scale) IPMB 6 19 BIT4 IPPB 7 18 BIT5 VPSIB 8 17 DENA 9 10 11 12 13 14 15 16 B B B CB MB NB PPB PMB DE OFS CCM VC O O DE VPSO NOTES
028
1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
07584- Figure 4. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1, 8, 13, 28 VPSIA, VPSIB, VPSOB, Input and Output Stage Positive Supply Voltage (4.75 V to 5.25 V). VPSOA 2, 3, 6, 7 IPPA, IPMA, IPMB, Differential Inputs. IPPB 4 ENBL Chip Enable. Pull this pin high to enable. 5, 20 ICOM, OCOM Input and Output Ground Pins. Connect these pins via the lowest possible impedance to ground. 9, 32 DECB, DECA VPOS/2 Reference Decoupling Node. Connect a decoupling capacitor from these nodes to ground. 10, 31 OFSB, OFSA Output Offset Correction Loop Compensation. Connect a capacitor from these nodes to ground to enable the correction loop. Tie this pin to ground to disable. 11, 30 CCMB, CCMA Connect These Nodes to Ground. 12, 29 VCMB, VCMA Output Common-Mode Setpoint. These pins default to VPOS/2 if left open. Drive these pins from a low impedance source to change the output common-mode voltage. 14, 15, 26, 27 OPPB, OPMB, OPMA, Differential Outputs. OPPA 16, 17 DENB, DENA Data Enable. Pull these pins high to address each or both channels for parallel gain programming. These pins are not used in serial mode. 18, 19, 21, 22, 23, 24 BIT5, BIT4, BIT3, Parallel Data Path (When SENB Is Low). When SENB is high, BIT0 becomes a chip select (CS), BIT2/SCLK, BIT1/SDAT, BIT1 becomes a serial data input (SDAT), and BIT2 becomes a serial clock (SCLK). BIT3 to BIT5 BIT0/CS are not used in serial mode. 25 SENB Serial Interface Enable. Pull this pin high for serial gain programming mode and pull this pin low for parallel gain programming mode. EPAD The exposed pad must be connected to ground. Rev. B | Page 7 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS PARALLEL AND SERIAL INTERFACE TIMING ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION INPUTS OUTPUTS OUTPUT DIFFERENTIAL OFFSET CORRECTION OUTPUT COMMON-MODE CONTROL GAIN CONTROL INTERFACE APPLICATIONS INFORMATION BASIC CONNECTIONS DIRECT CONVERSION RECEIVER DESIGN QUADRATURE ERRORS AND IMAGE REJECTION LOW FREQUENCY IMD3 PERFORMANCE BASEBAND INTERFACE CHARACTERIZATION SETUPS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
028
1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
07584- Figure 4. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1, 8, 13, 28 VPSIA, VPSIB, VPSOB, Input and Output Stage Positive Supply Voltage (4.75 V to 5.25 V). VPSOA 2, 3, 6, 7 IPPA, IPMA, IPMB, Differential Inputs. IPPB 4 ENBL Chip Enable. Pull this pin high to enable. 5, 20 ICOM, OCOM Input and Output Ground Pins. Connect these pins via the lowest possible impedance to ground. 9, 32 DECB, DECA VPOS/2 Reference Decoupling Node. Connect a decoupling capacitor from these nodes to ground. 10, 31 OFSB, OFSA Output Offset Correction Loop Compensation. Connect a capacitor from these nodes to ground to enable the correction loop. Tie this pin to ground to disable. 11, 30 CCMB, CCMA Connect These Nodes to Ground. 12, 29 VCMB, VCMA Output Common-Mode Setpoint. These pins default to VPOS/2 if left open. Drive these pins from a low impedance source to change the output common-mode voltage. 14, 15, 26, 27 OPPB, OPMB, OPMA, Differential Outputs. OPPA 16, 17 DENB, DENA Data Enable. Pull these pins high to address each or both channels for parallel gain programming. These pins are not used in serial mode. 18, 19, 21, 22, 23, 24 BIT5, BIT4, BIT3, Parallel Data Path (When SENB Is Low). When SENB is high, BIT0 becomes a chip select (CS), BIT2/SCLK, BIT1/SDAT, BIT1 becomes a serial data input (SDAT), and BIT2 becomes a serial clock (SCLK). BIT3 to BIT5 BIT0/CS are not used in serial mode. 25 SENB Serial Interface Enable. Pull this pin high for serial gain programming mode and pull this pin low for parallel gain programming mode. EPAD The exposed pad must be connected to ground. Rev. B | Page 7 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS PARALLEL AND SERIAL INTERFACE TIMING ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION INPUTS OUTPUTS OUTPUT DIFFERENTIAL OFFSET CORRECTION OUTPUT COMMON-MODE CONTROL GAIN CONTROL INTERFACE APPLICATIONS INFORMATION BASIC CONNECTIONS DIRECT CONVERSION RECEIVER DESIGN QUADRATURE ERRORS AND IMAGE REJECTION LOW FREQUENCY IMD3 PERFORMANCE BASEBAND INTERFACE CHARACTERIZATION SETUPS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
