Datasheet AD8372 (Analog Devices) - 10

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AD8372 Data Sheet THEORY OF OPERATION
The AD8372 is a dual differential variable gain amplifier. Each primarily to the use of differential signaling techniques to amplifier consists of a 150 Ω digitally control ed 6 dB attenuator cancel various distortion components in the device. In addition, fol owed by a 1 dB vernier and a fixed gain transconductance all ac characterization is done using differential signal paths. amplifier. Using this device with either the input or the output in a single- The differential output on each amplifier consists of a pair of ended circuit significantly degrades the overal performance of open-collector transistors. It is recommended that each open- the AD8372. col ector output be biased to +5 V with a high value inductor.
PASSIVE FILTER TECHNIQUES
A 33 μH inductor, such as the Coilcraft® 1812LS-333XJL, is an The AD8372 has a 100 Ω differential input impedance. For excellent choice for this component. A 250 Ω resistor should be optimal performance, the differential output load should be placed across the differential outputs to provide a current-to- 250 Ω. When designing passive filters around the AD8372, voltage conversion and as a source impedance for passive these impedances must be taken into account. filtering, post AD8372.
DIGITAL GAIN CONTROL
The gain for each side is based on a 250 Ω differential load and varies as the R The digital gain control interface consists of the following pins: LOAD changes per the following equations: SDI, SDO, CLK, and LATCH. The interface is active when the Gain = 20log(RLOAD/250), for voltage gain LATCH pin is shifted low. Gain words are written into the Gain = 10log(RLOAD/250), for power gain AD8372 via the SDI pin, and read back from the SDO pin. The The dependency of the gain on the load is due to the open- first bit clocked into the data input pin determines whether the collector output stage that is biased using external chokes. The interface is in write or read mode. The second bit is a don’t care inductance of the chokes and the resistance of the load deter- bit, while the remaining six bits program the gain. In read mine the low frequency pole of the amplifier. The high frequency mode, the SDO pin clocks out the 6-bit gain word, LSB to MSB. pole is set by the parasitic capacitance of the chokes and outputs The gain can be programmed between −9 dB and 32 dB in 1 dB in paral el with the output resistance. steps. Timing details are given in Figure 2 and Figure 3. The gain code is given in Table 2. The total supply current of 106 mA per side consists of 70 mA for the combined outputs and about 36 mA through the power
DRIVING ANALOG-TO-DIGITAL CONVERTERS
supply pins. Each side has an external resistor (REXT) to ground The AD8372 is designed with the intention of driving high to set the transconductance of the output stage. For optimum speed, high dynamic range ADCs. The circuit in Figure 14 distortion, 106 mA total current per side is recommended, represents a simplified front end of one-half of the AD8372 dual making the REXT value about 2.0 kΩ. Each side has a 2.4 V VGA driving an AD9445 14-bit, 125 MHz analog-to-digital reference pin and that same common-mode voltage appears on converter (ADC). The input of the AD8372 is driven the inputs. This reference should be decoupled using a 0.1 μF differential y using a 1:3 impedance ratio transformer, which capacitor. The part can be powered down to less than 2.6 mA by also matches the 150 Ω input resistance to a 50 Ω source. The setting the ENB pin low for the appropriate side. open-col ector outputs are biased through the 33 μH inductors The noise figure of the AD8372 is 7.8 dB at maximum gain and and are ac-coupled from the 142 Ω load resistors that, in increases as the gain is reduced. The increase in noise figure is paral el with the 2 kΩ input resistance of the ADC, provide a equal to the reduction in gain. 250 Ω load for gain accuracy. The linearity of the part measured at the output is first-order The ADC is ac-coupled from the 142 Ω resistors to negate a dc independent of the gain setting. effect on the input common-mode voltage of the AD9445. Including the series 33 Ω resistors improves the isolation of the Layout considerations should include minimizing capacitance AD8372 from the switching currents caused by the ADC input on the outputs by avoiding ground planes under the chokes, and sample and hold. The AD9445 represents a 2 kΩ differential equalizing the output line lengths for phase balance. load and requires a 2 V p-p signal when VREF = 1 V for a ful -
SINGLE-ENDED AND DIFFERENTIAL SIGNALS
scale output. This circuit provides variable gain, isolation, and The AD8372 is designed to be used by applying differential source matching for the AD9445. Using this circuit with the signals to the inputs and using the differential output drive of AD8372 in a gain of 32 dB (maximum gain), an SFDR the device to drive the next device in the signal chain. The performance of 74.5 dBc is achieved at 85 MHz (see Figure 15). excellent distortion performance of the AD8372 is due Rev. C | Page 10 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS SERIAL CONTROL INTERFACE TIMING ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SINGLE-ENDED AND DIFFERENTIAL SIGNALS PASSIVE FILTER TECHNIQUES DIGITAL GAIN CONTROL DRIVING ANALOG-TO-DIGITAL CONVERTERS EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE