Datasheet AD8376 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Ultralow Distortion IF Dual VGA |
| Pages / Page | 24 / 10 — AD8376. Data Sheet. REF3 POSITION. –600mV/DIV. REF3 SCALE. 500mV. 0pF. … |
| Revision | B |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
AD8376. Data Sheet. REF3 POSITION. –600mV/DIV. REF3 SCALE. 500mV. 0pF. 10pF EACH SIDE. INPUT. CH1 500mV Ω CH2 500mV Ω
Model Line for this Datasheet
Text Version of Document
AD8376 Data Sheet REF3 POSITION –600mV/DIV REF3 SCALE 500mV 0pF 10pF EACH SIDE INPUT 2 R1 R3 1
021 024
CH1 500mV Ω CH2 500mV Ω M10.0ns 10.0GS/s IT 10.0ps/pt M2.5ns 20.0GS/s IT 10.0ps/pt A CH1 960mV REF3 500mV 2.5ns A CH4 28.0mV
06725- 06725- Figure 22. Gain Step Time Domain Response Figure 25. Pulse Response to Capacitive Loading, Gain 20 dB
REF1 POSITION –1.08/DIV REF1 SCALE OUTPUT 50mV RISE (C2) 1.339ns FALL(C2) 1.367ns INPUT 2 2 REF1 1
025 06725- 022
CH1 500mV Ω CH2 500mV Ω M20.0ns 10.0GS/s IT 20.0ps/pt CH2 500mV M2.5ns 20Gsps A CH2 –590mV A CH1 960mV REF1 50.0mV IT 2.5ps/pt
06725- Figure 23. ENBL Time Domain Response Figure 26. Large Signal Pulse Response
0 180 REF1 POSITION –420mV/DIV REF1 SCALE 2V –5 120 0pF 10pF EACH SIDE –10 60 B) rees) d INPUT ( Deg –15 ( AG 0 E R1 R3 R4 11 M HAS S –20 –60 11 P S –25 –120 –180
023
–30 M2.5ns 20.0GS/s IT 10.0ps/pt 10 100 1000
026
REF 1 2.0V 2.5ns A CH4 28.0mV
06725-
FREQUENCY (MHz)
06725- Figure 24. Pulse Response to Capacitive Loading, Gain −4 dB Figure 27. S11 vs. Frequency Rev. B | Page 10 of 24 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Circuit Description Basic Structure Input System Output Amplifier Gain Control Applications Basic Connections Single-Ended-to-Differential Conversion Broadband Operation ADC Interfacing Layout Considerations Characterization Test Circuits Differential-to-Differential Characterization Evaluation Board Outline Dimensions Ordering Guide
021 024
CH1 500mV Ω CH2 500mV Ω M10.0ns 10.0GS/s IT 10.0ps/pt M2.5ns 20.0GS/s IT 10.0ps/pt A CH1 960mV REF3 500mV 2.5ns A CH4 28.0mV
06725- 06725- Figure 22. Gain Step Time Domain Response Figure 25. Pulse Response to Capacitive Loading, Gain 20 dB
REF1 POSITION –1.08/DIV REF1 SCALE OUTPUT 50mV RISE (C2) 1.339ns FALL(C2) 1.367ns INPUT 2 2 REF1 1
025 06725- 022
CH1 500mV Ω CH2 500mV Ω M20.0ns 10.0GS/s IT 20.0ps/pt CH2 500mV M2.5ns 20Gsps A CH2 –590mV A CH1 960mV REF1 50.0mV IT 2.5ps/pt
06725- Figure 23. ENBL Time Domain Response Figure 26. Large Signal Pulse Response
0 180 REF1 POSITION –420mV/DIV REF1 SCALE 2V –5 120 0pF 10pF EACH SIDE –10 60 B) rees) d INPUT ( Deg –15 ( AG 0 E R1 R3 R4 11 M HAS S –20 –60 11 P S –25 –120 –180
023
–30 M2.5ns 20.0GS/s IT 10.0ps/pt 10 100 1000
026
REF 1 2.0V 2.5ns A CH4 28.0mV
06725-
FREQUENCY (MHz)
06725- Figure 24. Pulse Response to Capacitive Loading, Gain −4 dB Figure 27. S11 vs. Frequency Rev. B | Page 10 of 24 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Circuit Description Basic Structure Input System Output Amplifier Gain Control Applications Basic Connections Single-Ended-to-Differential Conversion Broadband Operation ADC Interfacing Layout Considerations Characterization Test Circuits Differential-to-Differential Characterization Evaluation Board Outline Dimensions Ordering Guide
