Datasheet AD8367 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 500 MHz, 45 dB Linear-in-dB Variable Gain Amplifier |
| Pages / Page | 24 / 3 — AD8367. SPECIFICATIONS. Table 1. Parameter Conditions. Min. Typ. Max. Unit |
| Revision | A |
| File Format / Size | PDF / 498 Kb |
| Document Language | English |
AD8367. SPECIFICATIONS. Table 1. Parameter Conditions. Min. Typ. Max. Unit
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AD8367 SPECIFICATIONS
VS = 5 V, TA = 25°C, system impedance ZO = 200 Ω, VMODE = 5 V, f = 10 MHz, unless otherwise noted.
Table 1. Parameter Conditions Min Typ Max Unit
OVERALL FUNCTION Frequency Range LF 500 MHz GAIN Range 45 dB INPUT STAGE Pins INPT and ICOM Maximum Input To avoid input overload 700 mV p-p Input Resistance From INPT to ICOM 175 200 225 Ω GAIN CONTROL INTERFACE Pin GAIN Scaling Factor VMODE = 5 V, 50 mV ≤ VGAIN ≤ 950 mV +20 mV/dB VMODE = 0 V, 50 mV ≤ VGAIN ≤ 950 mV −20 mV/dB Gain Law Conformance 100 mV ≤ VGAIN ≤ 900 mV ±0.2 dB Maximum Gain VGAIN = 0.95 V +42.5 dB Minimum Gain VGAIN = 0.05 V −2.5 dB VGAIN Step Response From 0 dB to 30 dB 300 ns From 30 dB to 0 dB 300 ns Small Signal Bandwidth VGAIN = 0.5 V 5 MHz OUTPUT STAGE Pin VOUT Maximum Output Voltage Swing RL = 1 kΩ 4.3 V p-p RL = 200 Ω 3.5 V p-p Output Source Resistance Series resistance of output buffer 50 Ω Output Centering Voltage1 VS/2 V SQUARE LAW DETECTOR Pin DETO Output Set Point 354 mV rms AGC Small Signal Response Time CAGC = 100 pF, 6 dB gain step 1 μs POWER INTERFACE Pins VPSI, VPSO, ICOM, and OCOM Supply Voltage 2.7 5.5 V Total Supply Current ENBL high, maximum gain, RL = 200 Ω 26 30 mA (includes load current) Disable Current vs. Temperature ENBL low 1.3 1.6 mA −40°C ≤ TA ≤ +85°C 1.8 mA MODE CONTROL INTERFACE Pin MODE Mode LO Threshold Device in negative slope mode of operation 1.2 V Mode HI Threshold Device in positive slope mode of operation 1.4 V ENABLE INTERFACE Pin ENBL Enable Threshold 2.5 V Enable Response Time Time delay following LO to HI transition until 1.5 μs device meets full specifications. Enable Input Bias Current ENBL at 5 V 27 μA ENBL at 0 V 32 nA f = 70 MHz Gain Maximum gain +42.5 dB Minimum gain −3.7 dB Gain Scaling Factor 19.9 mV/dB Gain Intercept −5.6 dB Noise Figure Maximum gain 6.2 dB Output IP3 f1 = 70 MHz, f2 = 71 MHz, VGAIN = 0.5 V 36.5 dBm 29.5 dBV rms Output 1 dB Compression Point VGAIN = 0.5 V 8.5 dBm 1.5 dBV rms Rev. A | Page 3 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT ATTENUATOR AND GAIN CONTROL INPUT AND OUTPUT INTERFACES POWER AND VOLTAGE METRICS NOISE AND DISTORTION OUTPUT CENTERING RMS DETECTION APPLICATIONS INPUT AND OUTPUT MATCHING VGA OPERATION MODULATED GAIN MODE AGC OPERATION MODIFYING THE AGC SETPOINT EVALUATION BOARD CHARACTERIZATION SETUP AND METHODS OUTLINE DIMENSIONS ORDERING GUIDE
AD8367 SPECIFICATIONS
VS = 5 V, TA = 25°C, system impedance ZO = 200 Ω, VMODE = 5 V, f = 10 MHz, unless otherwise noted.
Table 1. Parameter Conditions Min Typ Max Unit
OVERALL FUNCTION Frequency Range LF 500 MHz GAIN Range 45 dB INPUT STAGE Pins INPT and ICOM Maximum Input To avoid input overload 700 mV p-p Input Resistance From INPT to ICOM 175 200 225 Ω GAIN CONTROL INTERFACE Pin GAIN Scaling Factor VMODE = 5 V, 50 mV ≤ VGAIN ≤ 950 mV +20 mV/dB VMODE = 0 V, 50 mV ≤ VGAIN ≤ 950 mV −20 mV/dB Gain Law Conformance 100 mV ≤ VGAIN ≤ 900 mV ±0.2 dB Maximum Gain VGAIN = 0.95 V +42.5 dB Minimum Gain VGAIN = 0.05 V −2.5 dB VGAIN Step Response From 0 dB to 30 dB 300 ns From 30 dB to 0 dB 300 ns Small Signal Bandwidth VGAIN = 0.5 V 5 MHz OUTPUT STAGE Pin VOUT Maximum Output Voltage Swing RL = 1 kΩ 4.3 V p-p RL = 200 Ω 3.5 V p-p Output Source Resistance Series resistance of output buffer 50 Ω Output Centering Voltage1 VS/2 V SQUARE LAW DETECTOR Pin DETO Output Set Point 354 mV rms AGC Small Signal Response Time CAGC = 100 pF, 6 dB gain step 1 μs POWER INTERFACE Pins VPSI, VPSO, ICOM, and OCOM Supply Voltage 2.7 5.5 V Total Supply Current ENBL high, maximum gain, RL = 200 Ω 26 30 mA (includes load current) Disable Current vs. Temperature ENBL low 1.3 1.6 mA −40°C ≤ TA ≤ +85°C 1.8 mA MODE CONTROL INTERFACE Pin MODE Mode LO Threshold Device in negative slope mode of operation 1.2 V Mode HI Threshold Device in positive slope mode of operation 1.4 V ENABLE INTERFACE Pin ENBL Enable Threshold 2.5 V Enable Response Time Time delay following LO to HI transition until 1.5 μs device meets full specifications. Enable Input Bias Current ENBL at 5 V 27 μA ENBL at 0 V 32 nA f = 70 MHz Gain Maximum gain +42.5 dB Minimum gain −3.7 dB Gain Scaling Factor 19.9 mV/dB Gain Intercept −5.6 dB Noise Figure Maximum gain 6.2 dB Output IP3 f1 = 70 MHz, f2 = 71 MHz, VGAIN = 0.5 V 36.5 dBm 29.5 dBV rms Output 1 dB Compression Point VGAIN = 0.5 V 8.5 dBm 1.5 dBV rms Rev. A | Page 3 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT ATTENUATOR AND GAIN CONTROL INPUT AND OUTPUT INTERFACES POWER AND VOLTAGE METRICS NOISE AND DISTORTION OUTPUT CENTERING RMS DETECTION APPLICATIONS INPUT AND OUTPUT MATCHING VGA OPERATION MODULATED GAIN MODE AGC OPERATION MODIFYING THE AGC SETPOINT EVALUATION BOARD CHARACTERIZATION SETUP AND METHODS OUTLINE DIMENSIONS ORDERING GUIDE
