Datasheet LT6553 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 650MHz Gain of 2 Triple Video Amplifier |
| Pages / Page | 12 / 8 — APPLICATIO S I FOR ATIO. Power Supplies. Input Considerations. not leave … |
| File Format / Size | PDF / 199 Kb |
| Document Language | English |
APPLICATIO S I FOR ATIO. Power Supplies. Input Considerations. not leave any supply pins disconnected or the part may
Model Line for this Datasheet
Text Version of Document
LT6553
U U W U APPLICATIO S I FOR ATIO Power Supplies
50% output) typically occurs in less than 50ns. Turn off is The LT6553 is optimized for ±5V supplies but can be slower, but is nonetheless below 300ns. operated on as little as ±2.25V or a single 4.5V supply and
Input Considerations
as much as ±6V or a single 12V supply. Internally, each supply is independent to improve channel isolation.
Do
The LT6553 input voltage range is from V– + 1V to V+ – 1V.
not leave any supply pins disconnected or the part may
Therefore, on split supplies the LT6553 input range is
not function correctly!
always larger than the output swing. On a single positive supply, however, the input range limits the output low
Enable/Shutdown
swing to 2V (1V multiplied by the internal gain of 2). The LT6553 has a TTL compatible shutdown mode con- The inputs can be driven beyond the point at which the trolled by the EN pin and referenced to the DGND pin. If the output clips so long as input currents are limited to below amplifier will be enabled at all times, the EN pin can be ±10mA. Continuing to drive the input beyond the output connected directly to DGND. If the enable function is limit can result in increased current drive and slightly desired, either driving the pin above 2V or allowing the increased swing, but will also increase supply current and internal 46k pull-up resistor to pull the EN pin to the top rail may result in delays in transient response at larger levels will disable the amplifier. When disabled, the DC output of overdrive. impedance will rise to approximately 700Ω through the internal feedback and gain resistors. Supply current into
Layout and Grounding
the amplifier in the disabled state will be primarily through It is imperative that care is taken in PCB layout in order to V+ and approximately equal to (V+ – V utilize the very high speed and very low crosstalk of the EN)/46k. It is important that the two following constraints on the LT6553. Separate power and ground planes are highly DGND pin and the EN pin are always followed: recommended and trace lengths should be kept as short as possible. If input or output traces must be run over a
V+ – VDGND
≥
3V
distance of several centimeters, they should use a con-
VEN – VDGND
≤
5.5V
trolled impedance with matching series and shunt resis- Split supplies of ±3V to ±5.5V will satisfy these require- tances (nominally 75Ω) to maintain signal fidelity. ments with DGND connected to 0V. Series termination resistors should be placed as close to In single supply applications above 5.5V, an additional the output pins as possible to minimize output capaci- resistor may be needed from the EN pin to DGND if the pin tance. See the Typical Performance Characteristics sec- is ever allowed to float. For example, on a 12V single tion for a plot of frequency response with various output supply, a 33k resistor would protect the pin from floating capacitors—only 10pF of parasitic output capacitance too high while still allowing the internal pull-up resistor to causes 6dB of peaking in the frequency response! disable the part. Low ESL/ESR bypass capacitors should be placed as close On dual ±2.25V supplies, connecting the EN and DGND to the positive and negative supply pins as possible. One pins to V– is the easiest way of ensuring that V+ – VDGND 4700pF ceramic capacitor is recommended for both V+ is more than 3V. and V–. Additional 470pF ceramic capacitors with minimal trace length on each supply pin will further improve AC and The DGND pin should not be pulled above the EN pin since transient response as well as channel isolation. For high doing so will turn on an ESD protection diode. If the EN pin current drive and large-signal transient applications, addi- voltage is forced a diode drop below the DGND pin, current tional 1µF to 10µF tantalums should be added on each should be limited to 10mA or less. supply. The smallest value capacitors should be placed The enable/disable times of the LT6553 are fast when closest to the package. driven with a logic input. Turn on (from 50% EN input to 6553f 8
U U W U APPLICATIO S I FOR ATIO Power Supplies
50% output) typically occurs in less than 50ns. Turn off is The LT6553 is optimized for ±5V supplies but can be slower, but is nonetheless below 300ns. operated on as little as ±2.25V or a single 4.5V supply and
Input Considerations
as much as ±6V or a single 12V supply. Internally, each supply is independent to improve channel isolation.
Do
The LT6553 input voltage range is from V– + 1V to V+ – 1V.
not leave any supply pins disconnected or the part may
Therefore, on split supplies the LT6553 input range is
not function correctly!
always larger than the output swing. On a single positive supply, however, the input range limits the output low
Enable/Shutdown
swing to 2V (1V multiplied by the internal gain of 2). The LT6553 has a TTL compatible shutdown mode con- The inputs can be driven beyond the point at which the trolled by the EN pin and referenced to the DGND pin. If the output clips so long as input currents are limited to below amplifier will be enabled at all times, the EN pin can be ±10mA. Continuing to drive the input beyond the output connected directly to DGND. If the enable function is limit can result in increased current drive and slightly desired, either driving the pin above 2V or allowing the increased swing, but will also increase supply current and internal 46k pull-up resistor to pull the EN pin to the top rail may result in delays in transient response at larger levels will disable the amplifier. When disabled, the DC output of overdrive. impedance will rise to approximately 700Ω through the internal feedback and gain resistors. Supply current into
Layout and Grounding
the amplifier in the disabled state will be primarily through It is imperative that care is taken in PCB layout in order to V+ and approximately equal to (V+ – V utilize the very high speed and very low crosstalk of the EN)/46k. It is important that the two following constraints on the LT6553. Separate power and ground planes are highly DGND pin and the EN pin are always followed: recommended and trace lengths should be kept as short as possible. If input or output traces must be run over a
V+ – VDGND
≥
3V
distance of several centimeters, they should use a con-
VEN – VDGND
≤
5.5V
trolled impedance with matching series and shunt resis- Split supplies of ±3V to ±5.5V will satisfy these require- tances (nominally 75Ω) to maintain signal fidelity. ments with DGND connected to 0V. Series termination resistors should be placed as close to In single supply applications above 5.5V, an additional the output pins as possible to minimize output capaci- resistor may be needed from the EN pin to DGND if the pin tance. See the Typical Performance Characteristics sec- is ever allowed to float. For example, on a 12V single tion for a plot of frequency response with various output supply, a 33k resistor would protect the pin from floating capacitors—only 10pF of parasitic output capacitance too high while still allowing the internal pull-up resistor to causes 6dB of peaking in the frequency response! disable the part. Low ESL/ESR bypass capacitors should be placed as close On dual ±2.25V supplies, connecting the EN and DGND to the positive and negative supply pins as possible. One pins to V– is the easiest way of ensuring that V+ – VDGND 4700pF ceramic capacitor is recommended for both V+ is more than 3V. and V–. Additional 470pF ceramic capacitors with minimal trace length on each supply pin will further improve AC and The DGND pin should not be pulled above the EN pin since transient response as well as channel isolation. For high doing so will turn on an ESD protection diode. If the EN pin current drive and large-signal transient applications, addi- voltage is forced a diode drop below the DGND pin, current tional 1µF to 10µF tantalums should be added on each should be limited to 10mA or less. supply. The smallest value capacitors should be placed The enable/disable times of the LT6553 are fast when closest to the package. driven with a logic input. Turn on (from 50% EN input to 6553f 8
