Datasheet LT6553 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 650MHz Gain of 2 Triple Video Amplifier |
| Pages / Page | 12 / 9 — APPLICATIO S I FOR ATIO. ESD Protection. TYPICAL APPLICATIO. RGB Buffer … |
| File Format / Size | PDF / 199 Kb |
| Document Language | English |
APPLICATIO S I FOR ATIO. ESD Protection. TYPICAL APPLICATIO. RGB Buffer Demo Board. Figure 1. DC714 Demo Board Schematic
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LT6553
U U W U APPLICATIO S I FOR ATIO
If the AGND pins are not connected directly to a low plane or power supply traces. Vias between topside and impedance ground plane, they must be carefully bypassed backside metal may be required to maintain a low to maintain minimal impedance over frequency. Pin 6 is a inductance ground near the part where numerous traces shared connection of the gain resistors of both channel G converge. and channel B, and any resistance external to this node can significantly decrease the isolation between those chan-
ESD Protection
nels. Although crosstalk will be very dependent on the The LT6553 has reverse-biased ESD protection diodes on board layout, a recommended starting point for bypass all pins. If any pins are forced a diode drop above the capacitors would be 470pF as close as possible to each positive supply or a diode drop below the negative supply, AGND pin with one 4700pF capacitor in parallel. large currents may flow through these diodes. If the current is kept below 10mA, no damage to the devices will To maintain the LT6553’s channel isolation, it is beneficial occur. to shield parallel input and output traces using a ground
U TYPICAL APPLICATIO RGB Buffer Demo Board
terminations are connected as close to the part as pos- sible. For ideal operation, a 75Ω load termination should The DC714 Demo Board illustrates optimal routing, be connected at the output. The LT6553’s gain of 2 will bypassing and termination using the LT6553 as an compensate for the resulting divider between the series RGB video buffer. The schematic is shown in Figure 1. All and load termination resistors. inputs and outputs are routed to have a characteristic impedance of 75Ω and 75Ω input shunt and output series E1 EN J1 50Ω BNC 1 JP1 EN CONTROL V+ 1 3 2 ENABLE EXT 5 4 3 2 V+ C1 C2 C3 C4 J2 JP2 4700pF 470pF 4700pF 10µF, 16V BANANA DGND 1210 JACK 1 3 LT6553 2 E2 1 16 EN V+ AGND FLOAT DGND NOTE 5 2 15 R1 BNC × 3 DGND V+ BNC x3 5 5 1 Z = 75 3 14 75Ω Z = 75 1 INR 4 4 INR OUTR OUTR 3 3 4 13 2 J5 R2 AGND V– J9 2 5 Z = 75 5 12 75Ω Z = 75 5 1 ING OUTG 1 ING 4 4 OUTG 3 6 11 R3 3 AGND V+ 2 J6 J10 2 Z = 75 7 10 75Ω Z = 75 5 INB OUTB 5 1 1 INB 4 4 R4 R5 R6 8 9 OUTB V– V– 3 3 75Ω 75Ω 75Ω 2 J7 J11 2 V– E3 AGND V– J4 SINGLE DUAL C5 C6 C7 C8 C9 BANANA JACK 1 2 3 470pF 1000pF 470pF 4700pF 10µF, 16V AGND 1210 J3 JP3 BANANA SUPPLY 5 JACK 5 1 Z = 75 1 CAL 4 4 CAL 3 3 2 J8 J12 2 BNC BNC
Figure 1. DC714 Demo Board Schematic
6553 F01 6553f 9
U U W U APPLICATIO S I FOR ATIO
If the AGND pins are not connected directly to a low plane or power supply traces. Vias between topside and impedance ground plane, they must be carefully bypassed backside metal may be required to maintain a low to maintain minimal impedance over frequency. Pin 6 is a inductance ground near the part where numerous traces shared connection of the gain resistors of both channel G converge. and channel B, and any resistance external to this node can significantly decrease the isolation between those chan-
ESD Protection
nels. Although crosstalk will be very dependent on the The LT6553 has reverse-biased ESD protection diodes on board layout, a recommended starting point for bypass all pins. If any pins are forced a diode drop above the capacitors would be 470pF as close as possible to each positive supply or a diode drop below the negative supply, AGND pin with one 4700pF capacitor in parallel. large currents may flow through these diodes. If the current is kept below 10mA, no damage to the devices will To maintain the LT6553’s channel isolation, it is beneficial occur. to shield parallel input and output traces using a ground
U TYPICAL APPLICATIO RGB Buffer Demo Board
terminations are connected as close to the part as pos- sible. For ideal operation, a 75Ω load termination should The DC714 Demo Board illustrates optimal routing, be connected at the output. The LT6553’s gain of 2 will bypassing and termination using the LT6553 as an compensate for the resulting divider between the series RGB video buffer. The schematic is shown in Figure 1. All and load termination resistors. inputs and outputs are routed to have a characteristic impedance of 75Ω and 75Ω input shunt and output series E1 EN J1 50Ω BNC 1 JP1 EN CONTROL V+ 1 3 2 ENABLE EXT 5 4 3 2 V+ C1 C2 C3 C4 J2 JP2 4700pF 470pF 4700pF 10µF, 16V BANANA DGND 1210 JACK 1 3 LT6553 2 E2 1 16 EN V+ AGND FLOAT DGND NOTE 5 2 15 R1 BNC × 3 DGND V+ BNC x3 5 5 1 Z = 75 3 14 75Ω Z = 75 1 INR 4 4 INR OUTR OUTR 3 3 4 13 2 J5 R2 AGND V– J9 2 5 Z = 75 5 12 75Ω Z = 75 5 1 ING OUTG 1 ING 4 4 OUTG 3 6 11 R3 3 AGND V+ 2 J6 J10 2 Z = 75 7 10 75Ω Z = 75 5 INB OUTB 5 1 1 INB 4 4 R4 R5 R6 8 9 OUTB V– V– 3 3 75Ω 75Ω 75Ω 2 J7 J11 2 V– E3 AGND V– J4 SINGLE DUAL C5 C6 C7 C8 C9 BANANA JACK 1 2 3 470pF 1000pF 470pF 4700pF 10µF, 16V AGND 1210 J3 JP3 BANANA SUPPLY 5 JACK 5 1 Z = 75 1 CAL 4 4 CAL 3 3 2 J8 J12 2 BNC BNC
Figure 1. DC714 Demo Board Schematic
6553 F01 6553f 9
