Datasheet ADP5302 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 50 mA/500 mA, Ultralow Power Step-Down Regulator with Battery Voltage Monitor |
| Pages / Page | 22 / 7 — Data Sheet. ADP5302. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. PIN 1. … |
| Revision | A |
| File Format / Size | PDF / 758 Kb |
| Document Language | English |
Data Sheet. ADP5302. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. PIN 1. INDICATOR. EN 1. 10 PVIN. STOP 2. 9 SW. SYNC/MODE 3. 8 PGND
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Data Sheet ADP5302 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR EN 1 10 PVIN STOP 2 9 SW ADP5302 SYNC/MODE 3 8 PGND TOP VIEW VID 4 (Not to Scale) 7 AGND
03 0
FB 5 6 VINOK
3- 344 1
NOTES 1. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A LARGE EXTERNAL COPPER GROUND PLANE UNDERNEATH THE IC FOR THERMAL DISSIPATION.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 EN Enable Input for the Regulator. A logic low on this pin disables the regulator. 2 STOP Stop Switching Input Signal. When this pin is logic high, the regulator stops switching. When this pin is logic low, the regulator resumes switching. 3 SYNC/MODE Synchronization Input Pin (SYNC). To synchronize the switching frequency of the device to an external clock, connect this pin to an external clock with a frequency from 1.5 MHz to 2.5 MHz. PWM or Hysteresis Mode Selection Pin (MODE). When this pin is logic high, the regulator operates in PWM mode. When this pin is logic low, the regulator operates in hysteresis mode. 4 VID Voltage Configuration Pin. Connect an external resistor (RVID) from this pin to ground to configure the output voltage of the regulator (see Table 5). 5 FB Feedback Sensing Input for the Regulator. 6 VINOK Input Power-Good Signal. This open-drain output is the power-good signal for the input voltage. 7 AGND Analog Ground. 8 PGND Power Ground. 9 SW Switching Node Output for the Regulator. 10 PVIN Power Input for the Regulator. EPAD EPAD Exposed Pad. Solder the exposed pad to a large external copper ground plane underneath the IC for thermal dissipation. Rev. A | Page 7 of 22 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode Hysteresis Mode Mode Selection OSCILLATOR AND SYNCHRONIZATION ADJUSTABLE AND FIXED OUTPUT VOLTAGES UNDERVOLTAGE LOCKOUT (UVLO) ENABLE/DISABLE CURRENT LIMIT SHORT-CIRCUIT PROTECTION SOFT START STARTUP WITH PRECHARGED OUTPUT 100% DUTY OPERATION ACTIVE DISCHARGE VINOK FUNCTION STOP SWITCHING THERMAL SHUTDOWN APPLICATIONS INFORMATION EXTERNAL COMPONENT SELECTION SELECTING THE INDUCTOR OUTPUT CAPACITOR INPUT CAPACITOR EFFICIENCY Power Switch Conduction Losses Inductor Losses Driver Losses Transition Losses PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADP5302 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR EN 1 10 PVIN STOP 2 9 SW ADP5302 SYNC/MODE 3 8 PGND TOP VIEW VID 4 (Not to Scale) 7 AGND
03 0
FB 5 6 VINOK
3- 344 1
NOTES 1. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A LARGE EXTERNAL COPPER GROUND PLANE UNDERNEATH THE IC FOR THERMAL DISSIPATION.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 EN Enable Input for the Regulator. A logic low on this pin disables the regulator. 2 STOP Stop Switching Input Signal. When this pin is logic high, the regulator stops switching. When this pin is logic low, the regulator resumes switching. 3 SYNC/MODE Synchronization Input Pin (SYNC). To synchronize the switching frequency of the device to an external clock, connect this pin to an external clock with a frequency from 1.5 MHz to 2.5 MHz. PWM or Hysteresis Mode Selection Pin (MODE). When this pin is logic high, the regulator operates in PWM mode. When this pin is logic low, the regulator operates in hysteresis mode. 4 VID Voltage Configuration Pin. Connect an external resistor (RVID) from this pin to ground to configure the output voltage of the regulator (see Table 5). 5 FB Feedback Sensing Input for the Regulator. 6 VINOK Input Power-Good Signal. This open-drain output is the power-good signal for the input voltage. 7 AGND Analog Ground. 8 PGND Power Ground. 9 SW Switching Node Output for the Regulator. 10 PVIN Power Input for the Regulator. EPAD EPAD Exposed Pad. Solder the exposed pad to a large external copper ground plane underneath the IC for thermal dissipation. Rev. A | Page 7 of 22 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode Hysteresis Mode Mode Selection OSCILLATOR AND SYNCHRONIZATION ADJUSTABLE AND FIXED OUTPUT VOLTAGES UNDERVOLTAGE LOCKOUT (UVLO) ENABLE/DISABLE CURRENT LIMIT SHORT-CIRCUIT PROTECTION SOFT START STARTUP WITH PRECHARGED OUTPUT 100% DUTY OPERATION ACTIVE DISCHARGE VINOK FUNCTION STOP SWITCHING THERMAL SHUTDOWN APPLICATIONS INFORMATION EXTERNAL COMPONENT SELECTION SELECTING THE INDUCTOR OUTPUT CAPACITOR INPUT CAPACITOR EFFICIENCY Power Switch Conduction Losses Inductor Losses Driver Losses Transition Losses PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
