Datasheet ADP5053 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Integrated Power Solution with Quad Buck Regulators and Supervisory Circuits |
| Pages / Page | 37 / 10 — ADP5053. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. DE O M. … |
| Revision | C |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
ADP5053. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. DE O M. MP3. NC/. MP1. SS3. SS1. BST3. 36 PVIN1. PGND3. 35 PVIN1. SW3. 34 SW1
Model Line for this Datasheet
Text Version of Document
ADP5053 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DE O M 4 MP3 2 EG NC/ MP1 N3 O B3 Y DD B1 O N1 E SS3 C F VR S V RT F C SS1 E 48 47 46 45 44 43 42 41 40 39 38 37 BST3 1 36 PVIN1 PGND3 2 35 PVIN1 SW3 3 34 SW1 PVIN3 4 33 SW1 WDI 5 ADP5053 32 BST1 VTH 6 31 DL1 TOP VIEW MR 7 30 PGND (Not to Scale) RSTO 8 29 DL2 PVIN4 9 28 BST2 SW4 10 27 SW2 PGND4 11 26 SW2 BST4 12 25 PVIN2 13 14 15 16 17 18 19 20 21 22 23 24 D 2 ND N4 B4 ND ND ND B2 N2 N E G MP4 F F G G G RG MP2 E O O PVI W C C P NOTES
003
1. THE EXPOSED PAD MUST BE CONNECTED AND SOLDERED TO AN EXTERNAL GROUND PLANE.
11636- Figure 3. Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
1 BST3 High-Side FET Driver Power Supply for Channel 3. 2 PGND3 Power Ground for Channel 3. 3 SW3 Switching Node Output for Channel 3. 4 PVIN3 Power Input for Channel 3. Connect a bypass capacitor between this pin and ground. 5 WDI Watchdog Refresh Input from Processor. 6 VTH Monitoring Voltage Threshold Programming. 7 MR Manual Reset Input, Active Low. 8 RSTO Open-Drain Reset Output, Active Low. 9 PVIN4 Power Input for Channel 4. Connect a bypass capacitor between this pin and ground. 10 SW4 Switching Node Output for Channel 4. 11 PGND4 Power Ground for Channel 4. 12 BST4 High-Side FET Driver Power Supply for Channel 4. 13 GND This pin is for internal test purposes. Connect this pin to ground. 14 EN4 Enable Input for Channel 4. Use an external resistor divider to set the turn-on threshold. 15 COMP4 Error Amplifier Output for Channel 4. Connect an RC network from this pin to ground. 16 FB4 Feedback Sensing Input for Channel 4. 17, 18, 19 GND These pins are for internal test purposes. Connect these pins to ground. 20 PWRGD Power-Good Signal Output. This open-drain output is the power-good signal for the selected channels. 21 FB2 Feedback Sensing Input for Channel 2. 22 COMP2 Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground. 23 EN2 Enable Input for Channel 2. Use an external resistor divider to set the turn-on threshold. 24, 25 PVIN2 Power Input for Channel 2. Connect a bypass capacitor between this pin and ground. 26, 27 SW2 Switching Node Output for Channel 2. 28 BST2 High-Side FET Driver Power Supply for Channel 2. 29 DL2 Low-Side FET Gate Driver for Channel 2. Connect a resistor from this pin to ground to program the current- limit threshold for Channel 2. 30 PGND Power Ground for Channel 1 and Channel 2. 31 DL1 Low-Side FET Gate Driver for Channel 1. Connect a resistor from this pin to ground to program the current- limit threshold for Channel 1. Rev. C | Page 10 of 37 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS SUPERVISORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES Pulse-Width Modulation (PWM) Mode Power Save Mode (PSM) Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN SUPERVISORY CIRCUIT Reset Output Watchdog Input Manual Reset Input Processor Manual Reset Mode Power On/Off Switch Mode APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
003
1. THE EXPOSED PAD MUST BE CONNECTED AND SOLDERED TO AN EXTERNAL GROUND PLANE.
11636- Figure 3. Pin Configuration
Table 7. Pin Function Descriptions Pin No. Mnemonic Description
1 BST3 High-Side FET Driver Power Supply for Channel 3. 2 PGND3 Power Ground for Channel 3. 3 SW3 Switching Node Output for Channel 3. 4 PVIN3 Power Input for Channel 3. Connect a bypass capacitor between this pin and ground. 5 WDI Watchdog Refresh Input from Processor. 6 VTH Monitoring Voltage Threshold Programming. 7 MR Manual Reset Input, Active Low. 8 RSTO Open-Drain Reset Output, Active Low. 9 PVIN4 Power Input for Channel 4. Connect a bypass capacitor between this pin and ground. 10 SW4 Switching Node Output for Channel 4. 11 PGND4 Power Ground for Channel 4. 12 BST4 High-Side FET Driver Power Supply for Channel 4. 13 GND This pin is for internal test purposes. Connect this pin to ground. 14 EN4 Enable Input for Channel 4. Use an external resistor divider to set the turn-on threshold. 15 COMP4 Error Amplifier Output for Channel 4. Connect an RC network from this pin to ground. 16 FB4 Feedback Sensing Input for Channel 4. 17, 18, 19 GND These pins are for internal test purposes. Connect these pins to ground. 20 PWRGD Power-Good Signal Output. This open-drain output is the power-good signal for the selected channels. 21 FB2 Feedback Sensing Input for Channel 2. 22 COMP2 Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground. 23 EN2 Enable Input for Channel 2. Use an external resistor divider to set the turn-on threshold. 24, 25 PVIN2 Power Input for Channel 2. Connect a bypass capacitor between this pin and ground. 26, 27 SW2 Switching Node Output for Channel 2. 28 BST2 High-Side FET Driver Power Supply for Channel 2. 29 DL2 Low-Side FET Gate Driver for Channel 2. Connect a resistor from this pin to ground to program the current- limit threshold for Channel 2. 30 PGND Power Ground for Channel 1 and Channel 2. 31 DL1 Low-Side FET Gate Driver for Channel 1. Connect a resistor from this pin to ground to program the current- limit threshold for Channel 1. Rev. C | Page 10 of 37 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS SUPERVISORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES Pulse-Width Modulation (PWM) Mode Power Save Mode (PSM) Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN SUPERVISORY CIRCUIT Reset Output Watchdog Input Manual Reset Input Processor Manual Reset Mode Power On/Off Switch Mode APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
