Datasheet ADP5051 (Analog Devices) - 4

ADP5051 Data Sheet FUNCTIONAL BLOCK DIAGRAM CHANNEL 1—BUCK UVLO1 PVIN1 0.8V
– +
EN1
+
A
–
CS1 1MΩ VREG
+
HICCUP BST1 AND Q1 CLK1 OCP
–
LATCH-UP DRIVER SLOPE COMP
+
E SW1 CMP1 CONTROL VREG G H COMP1
–
LOGIC C HAR IT AND MOSFET C S SW DI 0.8V
+
DRIVER WITH DRIVER DL1 EA1 CLK1 ANTICROSS
–
FB1 PROTECTION PGND FREQ ZERO FOLDBACK CROSS OVP
–
LATCH-UP VID1
+
0.88V CURRENT-LIMIT
+
SELECTION 0.72V
–
PWRGD1 CURRENT BALANCE EN2 CHANNEL 2—BUCK PVIN2 BST2 DUPLICATE COMP2 CHANNEL 1 DL2 FB2 SW2 VREG PVIN1 RT VREG OSCILLATOR INTERNAL REGULATOR SYNC/MODE VDD POWER-ON RESET SS12 HOUSE KEEPING VDDIO SOFT START LOGIC I2C AND DECODER REGISTERS SCL SS34 SDA PWRGD INT CHANNEL 3—BUCK UVLO3 PVIN3 0.8V
– +
EN3
+
A
–
CS3 1MΩ VREG
+
HICCUP BST3 AND OCP
–
LATCH-UP Q3 CLK3 DRIVER SLOPE COMP
+
CONTROL CMP3 SW3 COMP3
–
LOGIC AND MOSFET VREG Q4 0.8V DRIVER WITH
+
CLK3 ANTICROSS EA3 DRIVER
–
FB3 PROTECTION FREQ FOLDBACK PGND3 OVP ZERO E LATCH-UP CROSS
–
RG CHIT VID3
+
CHA 0.88V IS SW
+
D 0.72V
–
PWRGD3 EN4 CHANNEL 4—BUCK PVIN4 DUPLICATE BST4 COMP4 CHANNEL 3 SW4 FB4 PGND4 SUPERVISORY RSTO WDI WATCHDOG DETECTOR RESET GENERATOR
+
MR DEBOUNCE VTH
– -100
0.5V
635 11 Figure 2. Rev. B | Page 4 of 55 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS SUPERVISORY SPECIFICATIONS I2C INTERFACE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES Pulse-Width Modulation (PWM) Mode Power Save Mode (PSM) Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES DYNAMIC VOLTAGE SCALING (DVS) INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION INTERRUPT FUNCTION THERMAL SHUTDOWN OVERHEAT DETECTION LOW INPUT VOLTAGE DETECTION SUPERVISORY CIRCUIT Reset Output Watchdog Input Manual Reset Input Processor Manual Reset Mode Power On/Off Switch Mode I2C INTERFACE SDA AND SCL PINS I2C ADDRESSES SELF-CLEAR REGISTER BITS I2C INTERFACE TIMING DIAGRAMS APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS REGISTER MAP DETAILED REGISTER DESCRIPTIONS REGISTER 1: PCTRL (CHANNEL ENABLE CONTROL), ADDRESS 0x01 REGISTER 2: VID1 (VID SETTING FOR CHANNEL 1), ADDRESS 0x02 REGISTER 3: VID23 (VID SETTING FOR CHANNEL 2 AND CHANNEL 3), ADDRESS 0x03 REGISTER 4: VID4 (VID SETTING FOR CHANNEL 4), ADDRESS 0x04 REGISTER 5: DVS_CFG (DVS CONFIGURATION FOR CHANNEL 1 AND CHANNEL 4), ADDRESS 0x05 REGISTER 6: OPT_CFG (FPWM/PSM MODE AND OUTPUT DISCHARGE FUNCTION CONFIGURATION), ADDRESS 0x06 REGISTER 7: LCH_CFG (SHORT-CIRCUIT LATCH-OFF AND OVERVOLTAGE LATCH-OFF CONFIGURATION), ADDRESS 0x07 REGISTER 8: SW_CFG (SWITCHING FREQUENCY AND PHASE SHIFT CONFIGURATION), ADDRESS 0x08 REGISTER 9: TH_CFG (TEMPERATURE WARNING AND LOW VIN WARNING THRESHOLD CONFIGURATION), ADDRESS 0x09 REGISTER 10: HICCUP_CFG (HICCUP CONFIGURATION), ADDRESS 0x0A REGISTER 11: PWRGD_MASK (CHANNEL MASK CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B REGISTER 12: LCH_STATUS (LATCH-OFF STATUS READBACK), ADDRESS 0x0C REGISTER 13: STATUS_RD (STATUS READBACK), ADDRESS 0x0D REGISTER 14: INT_STATUS (INTERRUPT STATUS READBACK), ADDRESS 0x0E REGISTER 15: INT_MASK (INTERRUPT MASK CONFIGURATION), ADDRESS 0x0F REGISTER 16: FORCE_SHUT (FORCED SHUT DOWN), ADDRESS 0x10 REGISTER 17: DEFAULT_SET (DEFAULT RESET), ADDRESS 0x11 FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE