Datasheet ADP2116 (Analog Devices) - 4

ADP2116 Data Sheet Parameter Symbol Conditions Min Typ Max Unit
SYNC Pin Capacitance to GND CSYNC 5 pF SYNC Input Logic Low VIL_SYNC 0.8 V SYNC Input Logic High VIH_SYNC 2.0 V Phase Shift Between Channels 180 Degrees CLKOUT Frequency fCLKOUT fCLKOUT = 2 × fSW FREQ tied to GND 510 600 690 kHz FREQ via 8.2 kΩ to GND 1020 1200 1380 kHz FREQ via 27 kΩ to GND 2040 2400 2760 kHz CLKOUT Positive Pulse Time tCLKOUT 100 ns CLKOUT Rise or Fall Time CCLKOUT = 20 pF 10 ns CURRENT LIMIT All current-limit parameters provided for VDD = VINx = 2.75 V to 5.5 V Peak Output Current Limit, Channel 1 ILIMIT1 OPCFG tied to VDD or via 82 kΩ to GND 3.5 4.5 5.3 A Peak Output Current Limit, Channel 2 ILIMIT2 OPCFG tied to VDD or via 82 kΩ to GND 3.5 4.5 5.3 A OPCFG via 47 kΩ or 27 kΩ to GND 2.4 3.3 4.0 A Current-Sense Amplifier Gain GCS 4 A/V Hiccup Time fSW = 300 kHz 10 13.6 17 ms Number of Cumulative Current-Limit 8 Cycles Cycles to Go into Hiccup Mode SWITCH NODE CHARACTERISTICS High-Side, P-Channel R 1 DSON VDD = VINx = 3.3 V 68 mΩ VDD = VINx = 5.0 V 52 mΩ Low-Side, N-Channel R 1 DSON VDD = VINx = 3.3 V 32 mΩ VDD = VINx = 5.0 V 27 mΩ SWx Minimum On Time SWON MIN VDD = VINx = 2.75 V to 5.5 V 107 ns SWx Minimum Off Time SWOFF MIN VDD = VINx = 5.5 V 192 ns VDD = VINx = 2.75 V 255 ns SWx Maximum Leakage Current VDD = VINx = 2.75 V to 5.5 V, ENx = GND, 0.1 15 μA TJ = −40°C to +115°C ENABLE INPUTS EN1, EN2 Logic Low Level ENLO VDD = VINx = 2.75 V to 5.5 V 0.8 V EN1, EN2 Logic High Level ENHI VDD = VINx = 2.75 V to 5.5 V 2.0 V EN1, EN2 Input Leakage Current IEN_LEAK VDD = VINx = ENx = 2.75 V to 5.5 V, 0.1 1 μA TJ = −40°C to +115°C THERMAL SHUTDOWN Thermal Shutdown Threshold TTMSD 150 °C Thermal Shutdown Hysteresis 25 °C SOFT START SS1, SS2 Pin Current ISS1, ISS2 VDD = VINx = 2.75 V to 5.5 V, VSS = 0 V 4.8 6.0 7.8 μA Soft Start Threshold Voltage VSS_THRESH VDD = VINx = 2.75 V to 5.5 V 0.65 V Soft Start Pull-Down Current VDD = VINx = 2.75 V to 5.5 V, EN = GND 0.5 mA POWER GOOD All power-good parameters provided for VDD = VINx = 2.75 V to 5.5 V Overvoltage PGOODx Rising Threshold2 116 % Overvoltage PGOODx Falling Threshold2 100 108 114 % Undervoltage PGOODx Rising Threshold2 85 92 97 % Undervoltage PGOODx Falling Threshold2 84 % PGOODx Delay 50 μs PGOODx Leakage Current VPGOODx = VDD 0.1 1 μA PGOODx Low Saturation Voltage IPGOODx = 1 mA 50 110 mV 1 Pin-to-pin measurements. 2 The thresholds are expressed as a percentage of the nominal output voltage. Rev. B | Page 4 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS LINE AND LOAD REGULATION SUPPLY CURRENT LOAD TRANSIENT RESPONSE BASIC FUNCTIONALITY BODE PLOTS SIMPLIFIED BLOCK DIAGRAM THEORY OF OPERATION CONTROL ARCHITECTURE UNDERVOLTAGE LOCKOUT (UVLO) ENABLE/DISABLE CONTROL SOFT START POWER GOOD PULSE SKIP MODE HICCUP MODE CURRENT LIMIT THERMAL OVERLOAD PROTECTION MAXIMUM DUTY CYCLE OPERATION SYNCHRONIZATION CONVERTER CONFIGURATION SELECTING THE OUTPUT VOLTAGE SETTING THE OSCILLATOR FREQUENCY SYNCHRONIZATION AND CLKOUT OPERATION MODE CONFIGURATION EXTERNAL COMPONENTS SELECTION ADIsimPower DESIGN TOOL INPUT CAPACITOR SELECTION VDD RC FILTER INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION CONTROL LOOP COMPENSATION DESIGN EXAMPLE CHANNEL 1 CONFIGURATION AND COMPONENTS SELECTION CHANNEL 2 CONFIGURATION AND COMPONENTS SELECTION SYSTEM CONFIGURATION APPLICATION CIRCUITS POWER DISSIPATION AND THERMAL CONSIDERATIONS CIRCUIT BOARD LAYOUT RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE