Datasheet LT3507 (Analog Devices) - 9

LT3507
operation
The LT3507 contains three independent, constant fre- Each switcher contains an extra, independent oscillator to quency, current mode, switching regulators with internal perform frequency foldback during overload conditions. power switches plus a low dropout linear regulator. The This slave oscillator is normally synchronized to the master three regulators share common circuitry including input oscillator. A comparator senses when VFB is less than 50% source, voltage reference and oscillator, but are otherwise of its regulated value and switches the regulator from the independent. Operation can be best understood by refer- master oscillator to a slower slave oscillator. VFB is less than ring to the Block Diagram (Figure 1). 50% of its regulated value during start-up, short-circuit If the RUN pins are tied to ground, the LT3507 is shut and overload conditions. Frequency foldback helps limit down and draws <1µA from the input source tied to V switch current under these conditions. IN1. If any of the RUN pins are driven above 1V, the internal bias The TRK/SS pins override the 0.8V reference for the FB circuits turn on, including the internal regulator, reference, pins when the TRK/SS pins are below 0.8V. This allows and master oscillator. Each switching regulator will only either coincident or ratiometric supply tracking on start-up begin to operate when its corresponding RUN pin reaches as well as a soft-start capability. >1.25V. The master oscillator generates three clock signals, The switch drivers operate either from V with the signal for Channel 1 out of phase by 180°. IN or from the BOOST pin. An external capacitor and diode are used to The three switchers are current mode regulators. Instead generate a voltage at the BOOST pin that is higher than of directly modulating the duty cycle of the power switch, the input supply. This allows the driver to saturate the the feedback loop controls the peak current in the switch internal bipolar NPN power switch for efficient operation. during each cycle. Compared to voltage mode control, cur- The BIAS pin allows the internal circuitry to draw its current rent mode control improves loop dynamics and provides from a lower voltage supply than the input, also reducing cycle-by-cycle current limit. power dissipation and increasing efficiency. If the voltage The Block Diagram shows only one of the three step-down on the BIAS pin falls below 3V, then its quiescent current switching regulators. A pulse from the slave oscillator will flow from VIN. sets the RS flip-flop and turns on the internal NPN bipo- A power good comparator trips when the FB pin is at lar power switch. Current in the switch and the external 90% of its regulated value. The PGOOD output is an inductor begins to increase. When this current exceeds a open-collector transistor that is off when the output is in level determined by the voltage at VC, current comparator regulation, allowing an external resistor to pull the PGOOD C1 resets the flip-flop, turning off the switch. The current pin high. Power good is valid when the LT3507 is enabled in the inductor flows through the external Schottky diode and V and begins to decrease. The cycle begins again at the next IN > 3.5V. pulse from the oscillator. In this way, the voltage on the VC The LDO regulator uses an external NPN pass transistor to pin controls the current through the inductor to the output. form a linear regulator. The loop is internally compensated The internal error amplifier regulates the output voltage to be stable with a load capacitance of 2.2µF or greater. by continually adjusting the VC pin voltage. The threshold The LDO is disabled when all three of the RUN pins are low. for switching on the VC pin is >0.9V and an active clamp of 1.8V limits the output current. The overvoltage and undervoltage detection shuts down the LT3507 if the OVLO pin >1.2V or the UVLO pin <1.2V. Input overvoltage and undervoltage values are set by re- sistor dividers to VINSW. Hysteresis is provided by 10µA currents activated when either pin trips. The hysteresis voltage at VIN is the top resistor times 10µA. 3507fb For more information www.linear.com/LT3507 9