Datasheet LTC3419 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Dual Monolithic 600mA Synchronous Step-Down Regulator |
| Pages / Page | 16 / 8 — OPERATION. Main Control Loop. Dropout Operation. Light Load Operation. … |
| File Format / Size | PDF / 264 Kb |
| Document Language | English |
OPERATION. Main Control Loop. Dropout Operation. Light Load Operation. Soft-Start. Short-Circuit Protection
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LTC3419
OPERATION
The LTC3419 uses a constant-frequency, current mode MOSFET on. This cycle repeats at a rate that is dependent architecture. The operating frequency is set at 2.25MHz. on load demand. Both channels share the same clock and run in-phase. For applications where low ripple voltage and constant- The output voltage is set by an external resistor divider frequency operation is a higher priority than light load returned to the VFB pins. An error amplifi er compares the effi ciency, pulse-skipping mode can be used by connecting divided output voltage with a reference voltage of 0.6V and the MODE pin to VIN. In this mode, the peak inductor regulates the peak inductor current accordingly. current is not fi xed, which allows the LTC3419 to switch at a constant-frequency down to very low currents, where
Main Control Loop
it will begin skipping pulses. During normal operation, the top power switch (P-channel
Dropout Operation
MOSFET) is turned on at the beginning of a clock cycle when the VFB voltage is below the reference voltage. The When the input supply voltage decreases toward the current into the inductor and the load increases until the output voltage the duty cycle increases to 100%, which peak inductor current (controlled by ITH) is reached. The is the dropout condition. In dropout, the PMOS switch is RS latch turns off the synchronous switch and energy turned on continuously with the output voltage being equal stored in the inductor is discharged through the bottom to the input voltage minus the voltage drops across the switch (N-channel MOSFET) into the load until the next internal P-channel MOSFET and the inductor. clock cycle begins, or until the inductor current begins to An important design consideration is that the RDS(ON) reverse (sensed by the IRCMP comparator). of the P-channel switch increases with decreasing input The peak inductor current is controlled by the internally supply voltage (see Typical Performance Characteristics). compensated I Therefore, the user should calculate the worst-case power TH voltage, which is the output of the error amplifi er. This amplifi er regulates the V dissipation when the LTC3419 is used at 100% duty cycle FB pin to the internal 0.6V reference by adjusting the peak inductor current with low input voltage (see Thermal Considerations in the accordingly. Applications Information section).
Light Load Operation Soft-Start
There are two modes to control the LTC3419 at light load In order to minimize the inrush current on the input bypass currents: Burst Mode operation and pulse-skipping mode. capacitor, the LTC3419 slowly ramps up the output voltage Both automatically transition from continuous operation during start-up. Whenever the RUN1 or RUN2 pin is pulled to the selected mode when the load current is low. high, the corresponding output will ramp from zero to full-scale over a time period of approximately 750μs. This To optimize effi ciency, Burst Mode operation can be selected prevents the LTC3419 from having to quickly charge the by grounding the MODE pin. When the load is relatively output capacitor and thus supplying an excessive amount light, the peak inductor current (as set by ITH) remains of instantaneous current. fi xed at approximately 60mA and the PMOS switch operates intermittently based on load demand. By running cycles
Short-Circuit Protection
periodically, the switching losses are minimized. When either regulator output is shorted to ground, the The duration of each burst event can range from a few corresponding internal N-channel switch is forced on for cycles at light load to almost continuous cycling with a longer time period for each cycle in order to allow the short sleep intervals at moderate loads. During the sleep inductor to discharge, thus preventing inductor current intervals, the load current is being supplied solely from runaway. This technique has the effect of decreasing the output capacitor. As the output voltage droops, the switching frequency. Once the short is removed, normal error amplifi er output rises above the sleep threshold, operation resumes and the regulator output will return to signaling the burst comparator to trip and turn the top its nominal voltage. 3419fa 8
OPERATION
The LTC3419 uses a constant-frequency, current mode MOSFET on. This cycle repeats at a rate that is dependent architecture. The operating frequency is set at 2.25MHz. on load demand. Both channels share the same clock and run in-phase. For applications where low ripple voltage and constant- The output voltage is set by an external resistor divider frequency operation is a higher priority than light load returned to the VFB pins. An error amplifi er compares the effi ciency, pulse-skipping mode can be used by connecting divided output voltage with a reference voltage of 0.6V and the MODE pin to VIN. In this mode, the peak inductor regulates the peak inductor current accordingly. current is not fi xed, which allows the LTC3419 to switch at a constant-frequency down to very low currents, where
Main Control Loop
it will begin skipping pulses. During normal operation, the top power switch (P-channel
Dropout Operation
MOSFET) is turned on at the beginning of a clock cycle when the VFB voltage is below the reference voltage. The When the input supply voltage decreases toward the current into the inductor and the load increases until the output voltage the duty cycle increases to 100%, which peak inductor current (controlled by ITH) is reached. The is the dropout condition. In dropout, the PMOS switch is RS latch turns off the synchronous switch and energy turned on continuously with the output voltage being equal stored in the inductor is discharged through the bottom to the input voltage minus the voltage drops across the switch (N-channel MOSFET) into the load until the next internal P-channel MOSFET and the inductor. clock cycle begins, or until the inductor current begins to An important design consideration is that the RDS(ON) reverse (sensed by the IRCMP comparator). of the P-channel switch increases with decreasing input The peak inductor current is controlled by the internally supply voltage (see Typical Performance Characteristics). compensated I Therefore, the user should calculate the worst-case power TH voltage, which is the output of the error amplifi er. This amplifi er regulates the V dissipation when the LTC3419 is used at 100% duty cycle FB pin to the internal 0.6V reference by adjusting the peak inductor current with low input voltage (see Thermal Considerations in the accordingly. Applications Information section).
Light Load Operation Soft-Start
There are two modes to control the LTC3419 at light load In order to minimize the inrush current on the input bypass currents: Burst Mode operation and pulse-skipping mode. capacitor, the LTC3419 slowly ramps up the output voltage Both automatically transition from continuous operation during start-up. Whenever the RUN1 or RUN2 pin is pulled to the selected mode when the load current is low. high, the corresponding output will ramp from zero to full-scale over a time period of approximately 750μs. This To optimize effi ciency, Burst Mode operation can be selected prevents the LTC3419 from having to quickly charge the by grounding the MODE pin. When the load is relatively output capacitor and thus supplying an excessive amount light, the peak inductor current (as set by ITH) remains of instantaneous current. fi xed at approximately 60mA and the PMOS switch operates intermittently based on load demand. By running cycles
Short-Circuit Protection
periodically, the switching losses are minimized. When either regulator output is shorted to ground, the The duration of each burst event can range from a few corresponding internal N-channel switch is forced on for cycles at light load to almost continuous cycling with a longer time period for each cycle in order to allow the short sleep intervals at moderate loads. During the sleep inductor to discharge, thus preventing inductor current intervals, the load current is being supplied solely from runaway. This technique has the effect of decreasing the output capacitor. As the output voltage droops, the switching frequency. Once the short is removed, normal error amplifi er output rises above the sleep threshold, operation resumes and the regulator output will return to signaling the burst comparator to trip and turn the top its nominal voltage. 3419fa 8
