Datasheet LTC3407-3 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual Synchronous, 1.8V/0.8A and 3.3V/0.8A 2.25MHz Step-Down DC/DC Regulator |
| Pages / Page | 16 / 10 — APPLICATIONS INFORMATION. Checking Transient Response. Power-On Reset. … |
| File Format / Size | PDF / 269 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Checking Transient Response. Power-On Reset. Mode Selection & Frequency Synchronization
Model Line for this Datasheet
Text Version of Document
LTC3407-3
APPLICATIONS INFORMATION
Since the ESR of a ceramic capacitor is so low, the input ing this pin to VIN enables Burst Mode operation, which and output capacitor must instead fulfi ll a charge storage provides the best low current effi ciency at the cost of a requirement. During a load step, the output capacitor must higher output voltage ripple. Connecting this pin to ground instantaneously supply the current to support the load selects pulse-skipping mode, which provides the lowest until the feedback loop raises the switch current enough output ripple, at the cost of low current effi ciency. to support the load. The time required for the feedback The LTC3407-3 can also be synchronized to an external loop to respond is dependent on the compensation and 2.25MHz clock signal (such as the SW pin on another the output capacitor size. Typically, 3-4 cycles are required LTC3407-3) by the MODE/SYNC pin. During synchro- to respond to a load step, but only in the fi rst cycle does nization, the mode is set to pulse-skipping and the top the output drop linearly. The output droop, VDROOP, is switch turn-on is synchronized to the rising edge of the usually about 2-3 times the linear drop of the fi rst cycle. external clock. Thus, a good place to start is with the output capacitor size of approximately:
Checking Transient Response
ΔI C OUT The regulator loop response can be checked by looking OUT ≈ 2.5 f • V O DROOP at the load transient response. Switching regulators take More capacitance may be required depending on the duty several cycles to respond to a step in load current. When cycle and load step requirements. a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESR, where ESR is the effective series In most applications, the input capacitor is merely required resistance of COUT. ΔILOAD also begins to charge or dis- to supply high frequency bypassing, since the impedance charge COUT, generating a feedback error signal used by the to the supply is very low. A 10μF ceramic capacitor is regulator to return VOUT to its steady-state value. During usually enough for these conditions. this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The initial
Power-On Reset
output voltage step may not be within the bandwidth of the The POR pin is an open-drain output which pulls low when feedback loop, so the standard second-order overshoot/DC either regulator is out of regulation. When both output volt- ratio cannot be used to determine phase margin. ages are above –8.5% of regulation, a timer is started which releases POR after 218 clock cycles (about 117ms). This The output voltage settling behavior is related to the stability delay can be signifi cantly longer in Burst Mode operation of the closed-loop system and will demonstrate the actual with low load currents, since the clock cycles only occur overall supply performance. For a detailed explanation of during a burst and there could be milliseconds of time optimizing the compensation components, including a re- between bursts. This can be bypassed by tying the POR view of control loop theory, refer to Application Note 76. output to the MODE/SYNC input, to force pulse-skipping In some applications, a more severe transient can be caused mode during a reset. In addition, if the output voltage by switching in loads with large (>1μF) input capacitors. faults during Burst Mode sleep, POR could have a slight The discharged input capacitors are effectively put in paral- delay for an undervoltage output condition and may not lel with C respond to an overvoltage output. This can be avoided by OUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem, if the using pulse-skipping mode instead. When either channel switch connecting the load has low resistance and is driven is shut down, the POR output is pulled low, since one or quickly. The solution is to limit the turn-on speed of the both of the channels are not in regulation. load switch driver. A Hot Swap™ controller is designed
Mode Selection & Frequency Synchronization
specifi cally for this purpose and usually incorporates cur- rent limiting, short-circuit protection, and soft-starting. The MODE/SYNC pin is a multipurpose pin which provides mode selection and frequency synchronization. Connect- Hot Swap is a trademark of Linear Technology Corporation. 34073fb 10
APPLICATIONS INFORMATION
Since the ESR of a ceramic capacitor is so low, the input ing this pin to VIN enables Burst Mode operation, which and output capacitor must instead fulfi ll a charge storage provides the best low current effi ciency at the cost of a requirement. During a load step, the output capacitor must higher output voltage ripple. Connecting this pin to ground instantaneously supply the current to support the load selects pulse-skipping mode, which provides the lowest until the feedback loop raises the switch current enough output ripple, at the cost of low current effi ciency. to support the load. The time required for the feedback The LTC3407-3 can also be synchronized to an external loop to respond is dependent on the compensation and 2.25MHz clock signal (such as the SW pin on another the output capacitor size. Typically, 3-4 cycles are required LTC3407-3) by the MODE/SYNC pin. During synchro- to respond to a load step, but only in the fi rst cycle does nization, the mode is set to pulse-skipping and the top the output drop linearly. The output droop, VDROOP, is switch turn-on is synchronized to the rising edge of the usually about 2-3 times the linear drop of the fi rst cycle. external clock. Thus, a good place to start is with the output capacitor size of approximately:
Checking Transient Response
ΔI C OUT The regulator loop response can be checked by looking OUT ≈ 2.5 f • V O DROOP at the load transient response. Switching regulators take More capacitance may be required depending on the duty several cycles to respond to a step in load current. When cycle and load step requirements. a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESR, where ESR is the effective series In most applications, the input capacitor is merely required resistance of COUT. ΔILOAD also begins to charge or dis- to supply high frequency bypassing, since the impedance charge COUT, generating a feedback error signal used by the to the supply is very low. A 10μF ceramic capacitor is regulator to return VOUT to its steady-state value. During usually enough for these conditions. this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The initial
Power-On Reset
output voltage step may not be within the bandwidth of the The POR pin is an open-drain output which pulls low when feedback loop, so the standard second-order overshoot/DC either regulator is out of regulation. When both output volt- ratio cannot be used to determine phase margin. ages are above –8.5% of regulation, a timer is started which releases POR after 218 clock cycles (about 117ms). This The output voltage settling behavior is related to the stability delay can be signifi cantly longer in Burst Mode operation of the closed-loop system and will demonstrate the actual with low load currents, since the clock cycles only occur overall supply performance. For a detailed explanation of during a burst and there could be milliseconds of time optimizing the compensation components, including a re- between bursts. This can be bypassed by tying the POR view of control loop theory, refer to Application Note 76. output to the MODE/SYNC input, to force pulse-skipping In some applications, a more severe transient can be caused mode during a reset. In addition, if the output voltage by switching in loads with large (>1μF) input capacitors. faults during Burst Mode sleep, POR could have a slight The discharged input capacitors are effectively put in paral- delay for an undervoltage output condition and may not lel with C respond to an overvoltage output. This can be avoided by OUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem, if the using pulse-skipping mode instead. When either channel switch connecting the load has low resistance and is driven is shut down, the POR output is pulled low, since one or quickly. The solution is to limit the turn-on speed of the both of the channels are not in regulation. load switch driver. A Hot Swap™ controller is designed
Mode Selection & Frequency Synchronization
specifi cally for this purpose and usually incorporates cur- rent limiting, short-circuit protection, and soft-starting. The MODE/SYNC pin is a multipurpose pin which provides mode selection and frequency synchronization. Connect- Hot Swap is a trademark of Linear Technology Corporation. 34073fb 10
