Datasheet LTC3404 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 1.4MHz High Efficiency Monolithic Synchronous Step-Down Regulator |
| Pages / Page | 16 / 7 — FU CTIO AL DIAGRA. OPERATIO. Main Control Loop. Burst Mode Operation |
| File Format / Size | PDF / 215 Kb |
| Document Language | English |
FU CTIO AL DIAGRA. OPERATIO. Main Control Loop. Burst Mode Operation
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Text Version of Document
LTC3404
U U W FU CTIO AL DIAGRA
VIN BURST Y = “0” ONLY WHEN X IS A CONSTANT “1” Y DEFEAT X PLL LPF 8 SLOPE SYNC/MODE COMP 7 0.8V VCO OSC 0.6V – FREQ 6 VIN 3 + SHIFT – VFB + – EN SLEEP V + REF 6Ω 0.8V 0.55V + – + I – EA COMP BURST VIN SLEEP Ω S Q gm = 0.5m VIN R Q SWITCHING V 2 ITH RS LATCH IN LOGIC P-CH P-CH AND ANTI- SHOOT- RUN BLANKING CIRCUIT THRU 5 SW 1 0.8V REF – OVDET 0.85V + + N-CH SHUTDOWN IRCMP– 4 GND 3404 BD
U OPERATIO Main Control Loop
the current reversal comparator IRCMP, or the beginning of The LTC3404 uses a constant frequency, current mode the next clock cycle. step-down architecture. Both the main (P-channel MOS- Comparator OVDET guards against transient overshoots FET) and synchronous (N-channel MOSFET) switches are >6.25% by turning the main switch off and keeping it off internal. During normal operation, the internal top power until the fault is removed. MOSFET is turned on each clock cycle when the oscillator sets the RS latch, and turned off when the current com-
Burst Mode Operation
parator, ICOMP, resets the RS latch. The peak inductor The LTC3404 is capable of Burst Mode operation in which current at which ICOMP resets the RS latch is controlled by the internal power MOSFETs operate intermittently based the voltage on the ITH pin, which is the output of error on load demand. To enable Burst Mode operation, simply amplifier EA. The VFB pin, described in the Pin Functions tie the SYNC/MODE pin to VIN or connect it to a logic high section, allows EA to receive an output feedback voltage (VSYNC/MODE > 1.5V). To disable Burst Mode operation and from an external resistive divider. When the load current enable PWM pulse skipping mode, connect the SYNC/ increases, it causes a slight decrease in the feedback MODE pin to GND. In this mode, the efficiency is lower at voltage, VFB, relative to the 0.8V internal reference, which light loads, but becomes comparable to Burst Mode in turn, causes the ITH voltage to increase until the average operation when the output load exceeds 50mA. The ad- inductor current matches the new load current. While the vantage of pulse skipping mode is lower output ripple and top MOSFET is off, the bottom MOSFET is turned on until less interference to audio circuitry. either the inductor current starts to reverse as indicated by 3404fb 7
U U W FU CTIO AL DIAGRA
VIN BURST Y = “0” ONLY WHEN X IS A CONSTANT “1” Y DEFEAT X PLL LPF 8 SLOPE SYNC/MODE COMP 7 0.8V VCO OSC 0.6V – FREQ 6 VIN 3 + SHIFT – VFB + – EN SLEEP V + REF 6Ω 0.8V 0.55V + – + I – EA COMP BURST VIN SLEEP Ω S Q gm = 0.5m VIN R Q SWITCHING V 2 ITH RS LATCH IN LOGIC P-CH P-CH AND ANTI- SHOOT- RUN BLANKING CIRCUIT THRU 5 SW 1 0.8V REF – OVDET 0.85V + + N-CH SHUTDOWN IRCMP– 4 GND 3404 BD
U OPERATIO Main Control Loop
the current reversal comparator IRCMP, or the beginning of The LTC3404 uses a constant frequency, current mode the next clock cycle. step-down architecture. Both the main (P-channel MOS- Comparator OVDET guards against transient overshoots FET) and synchronous (N-channel MOSFET) switches are >6.25% by turning the main switch off and keeping it off internal. During normal operation, the internal top power until the fault is removed. MOSFET is turned on each clock cycle when the oscillator sets the RS latch, and turned off when the current com-
Burst Mode Operation
parator, ICOMP, resets the RS latch. The peak inductor The LTC3404 is capable of Burst Mode operation in which current at which ICOMP resets the RS latch is controlled by the internal power MOSFETs operate intermittently based the voltage on the ITH pin, which is the output of error on load demand. To enable Burst Mode operation, simply amplifier EA. The VFB pin, described in the Pin Functions tie the SYNC/MODE pin to VIN or connect it to a logic high section, allows EA to receive an output feedback voltage (VSYNC/MODE > 1.5V). To disable Burst Mode operation and from an external resistive divider. When the load current enable PWM pulse skipping mode, connect the SYNC/ increases, it causes a slight decrease in the feedback MODE pin to GND. In this mode, the efficiency is lower at voltage, VFB, relative to the 0.8V internal reference, which light loads, but becomes comparable to Burst Mode in turn, causes the ITH voltage to increase until the average operation when the output load exceeds 50mA. The ad- inductor current matches the new load current. While the vantage of pulse skipping mode is lower output ripple and top MOSFET is off, the bottom MOSFET is turned on until less interference to audio circuitry. either the inductor current starts to reverse as indicated by 3404fb 7
