Datasheet LTC3802 (Analog Devices) - 9

LTC3802
U U U PI FU CTIO S (28-Pin SSOP/32-Pin QFN Package) FBT (Pin 8/Pin 5):
Feedback Tracking Input. FBT should be
FCB (Pin 13/Pin 10):
Force Continuous Bar. Internally connected through a resistive divider network to VOUT1 to pulled high. When FCB is shorted to GND, the controller set the channel 1 output slew rate. Upon power-up/-down, forces both converters to maintain continuous synchro- the LTC3802 servos FBT and CMPIN2 to the same poten- nous operation regardless of load current. tial to control the output power-up/-down slew rate. To
EXTREF (Pin 11, QFN Package Only):
External Reference. program both outputs to have the same slew rate, dupli- The EXTREF pin and the internal bandgap voltage are used cate the CMPIN2 resistive divider at FBT. To have a as the switcher control loop’s reference in a diode OR ratiometric slew rate, short FBT to CMPIN1. To disable the manner. If the potential at the EXTREF pin is less than 0.6V, tracking function, short FBT to CMPIN2. it overrides the internal reference and lowers the switcher
CMPIN1 (Pin 9/Pin 6):
Channel 1 Controller Comparators output voltages. If EXTREF potential is more than 1V, the Input. CMPIN1 should be connected through a resistive internal bandgap voltage controls both channel output divider network to VOUT1 to monitor its real time output voltages. EXTREF has no effect on the PGOOD threshold. voltage. To improve transient response, a feedforward EXTREF is internally connected to the RUN/SS pin in the capacitor can be added to the resistive divider. The power GN28 package. good comparators, overvoltage comparator and Burst
RUN/SS (Pin 14/Pin 12):
Run Control and Soft-Start reset comparators monitor this node directly. CMPIN1 is Input. An internal 7µA current source pull-up and an a sensitive pin, avoid coupling noise into this pin. external capacitor to ground at this pin sets the start-up
COMP1 (Pin 10/Pin 7):
Channel 1 Controller Error Ampli- delaly (approximately 300ms/µF), the output ramp rate fier Output. The COMP1 pin is connected directly to the and the time delay for soft current limit. Forcing this pin channel 1 error amplifier output and the input of the line below 0.8V with an open-drain/collector transistor shuts feedforward circuit. Use an RC network between the down the device. Pulling RUN/SS high with a current COMP1 pin and the FB1 pin to compensate the feedback greater than 10µA can result in malfunctioning of tracking loop for optimum transient response. Under start-up during start-up. Pulling RUN/SS high with currents higher conditions, the potential at RUN/SS controls the slew rate than 50µA can interfere with current limit protection. at COMP1.
PGOOD (Pin 15/Pin 13):
Open-Drain Power Good Output.
FB1 (Pin 11/Pin 8):
Channel 1 Controller Error Amplifier PGOOD is pulled to ground under shutdown condition or Input. FB1 should be connected through a resistive divider when any switcher output voltage is not within ±10% of its network to VOUT1 to set the channel 1 switcher output set point . voltage. Also, connect the channel 1 switcher loop com-
V
pensation network to FB1.
INFF (Pin 16/Pin 14):
Line Feedforward Compensation Input. Connects to the VIN power supply to provide line
SGND (Pin 12/Pin 9):
Signal Ground. All the internal low feedforward compensation. A change in VIN immediately power circuitry returns to the SGND pin. Connect to a low modulates the input to the PWM comparator and changes impedance ground, separated from the PGND node. All the pulse width in an inversely proportional manner, thus feedback, compensation and soft-start connections should bypassing the feedback loop and providing excellent tran- return to SGND. SGND and PGND should be connected sient line regulation. VINFF is a sensitive pin, an external only at a single point, near the PGND pin and the negative lowpass filter can be added to this pin to prevent noisy terminal of the VIN bypass capacitor. signals from affecting the loop gain. 3802f 9